PN5120A0HN/C1 NXP Semiconductors, PN5120A0HN/C1 Datasheet - Page 69

• Manufacturer Part Number: PN5120A0HN/C1
• Description: Transmission Module 40-Pin HVQFN EP T/R
• Manufacturer: NXP Semiconductors

Specifications of PN5120A0HN/C1

• Package: 40HVQFN EP
• Operating Temperature: -30 to 85 °C

NXP Semiconductors
PN512
Product data sheet
COMPANY PUBLIC
Fig 14. UART read data timing diagram
DTRQ
(1) Reserved.
MX
RX
TX
SA
A0
Remark: The LSB for data and address bytes must be sent first. No parity bit is used
during transmission.
Read data: To read data using the UART interface, the flow shown in
used. The first byte sent defines both the mode and the address.
Table 148. Read data byte order
Write data: To write data to the PN512 using the UART interface, the structure shown in
Table 149
The first byte sent defines both the mode and the address.
Table 149. Write data byte order
Pin
RX (pin 24)
TX (pin 31)
Pin
RX (pin 24)
TX (pin 31)
A1
A2
must be used.
ADDRESS
A3
All information provided in this document is subject to legal disclaimers.
A4
Byte 0
address
-
Byte 0
address 0
-
Rev. 3.6 — 10 March 2011
A5
(1)
111336
R/W
SA
SO
D0
D1
D2
D3
DATA
Byte 1
-
data 0
Byte 1
data 0
address 0
D4
D5
Transmission module
D6
Table 148
© NXP B.V. 2011. All rights reserved.
D7
PN512
SO
001aak588
must be
69 of 125