PN5120A0HN/C1 NXP Semiconductors, PN5120A0HN/C1 Datasheet - Page 41
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PN5120A0HN/C1
Manufacturer Part Number
PN5120A0HN/C1
Description
Transmission Module 40-Pin HVQFN EP T/R
Manufacturer
NXP Semiconductors
Datasheet
1.PN5120A0HN1C2118.pdf
(125 pages)
Specifications of PN5120A0HN/C1
Package
40HVQFN EP
Operating Temperature
-30 to 85 °C
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Product data sheet
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9.2.2.10 DemodReg
Defines demodulator settings.
Table 64.
Table 65.
Bit
7 to 6
5
4
3 to 2
1 to 0
Access
Rights
Symbol
AddIQ
FixIQ
TPrescalE
ven
TauRcv
TauSync
DemodReg register (address 19h); reset value: 4Dh, 01001101b
Description of DemodReg bits
r/w
7
All information provided in this document is subject to legal disclaimers.
AddIQ
Description
Defines the use of I and Q channel during reception
Note: FixIQ has to be set to logic 0 to
enable the following settings.
Value
00
01
10
11
If set to logic 1 and the bits of AddIQ are set to X0, the reception is fixed to
I channel.
If set to logic 1 and the bits of AddIQ are set to X1, the reception is fixed to
Q channel.
NOTE: If SIGIN/SIGOUT is used as S2C interface FixIQ set to 1 and AddIQ
set to X0 is rewired.
If set to logic 0 the following formula is used to calculate fTimer of the
prescaler:
If set to logic 1 the following formula is used to calculate fTimer of the
prescaler:
Changes the time constant of the internal during data reception.
Note: If set to 00, the PLL is frozen during data reception.
Changes the time constant of the internal PLL during burst.
Rev. 3.6 — 10 March 2011
f
fTimer = 13.56 MHz / (2 * TPreScaler + 2).
(Default TPrescalEven is logic 0)
r/w
Timer
6
= 13.56 MHz / (2 * TPreScaler + 1).
Description
Select the stronger channel
Select the stronger and freeze the selected during communication
combines the I and Q channel
Reserved
111336
FixIQ
r/w
5
TPrescal
Even
r/w
4
r/w
3
TauRcv
r/w
2
Transmission module
© NXP B.V. 2011. All rights reserved.
r/w
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TauSync
PN512
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