PN5120A0HN/C1 NXP Semiconductors, PN5120A0HN/C1 Datasheet - Page 120

• Manufacturer Part Number: PN5120A0HN/C1
• Description: Transmission Module 40-Pin HVQFN EP T/R
• Manufacturer: NXP Semiconductors

Specifications of PN5120A0HN/C1

• Package: 40HVQFN EP
• Operating Temperature: -30 to 85 °C

NXP Semiconductors
34. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. Communication overview for Passive
Table 11. Framing and coding overview. . . . . . . . . . . . . .16
Table 12. MIFARE Card operation mode . . . . . . . . . . . . .16
Table 13. FeliCa Card operation mode . . . . . . . . . . . . . .17
Table 14. PN512 registers overview . . . . . . . . . . . . . . . .17
Table 15. Behavior of register bits and its designation . . .19
Table 16. PageReg register (address 00h); reset value: 00h,
Table 17. Description of PageReg bits . . . . . . . . . . . . . . .20
Table 18. CommandReg register (address 01h); reset
Table 19. Description of CommandReg bits . . . . . . . . . . .20
Table 20. CommIEnReg register (address 02h); reset value:
Table 21. Description of CommIEnReg bits . . . . . . . . . . .21
Table 22. DivIEnReg register (address 03h); reset value:
Table 23. Description of DivIEnReg bits . . . . . . . . . . . . . .22
Table 24. CommIRqReg register (address 04h); reset value:
Table 25. Description of CommIRqReg bits . . . . . . . . . . .23
Table 26. DivIRqReg register (address 05h); reset value:
Table 27. Description of DivIRqReg bits . . . . . . . . . . . . .24
Table 28. ErrorReg register (address 06h); reset value: 00h,
Table 29. Description of ErrorReg bits . . . . . . . . . . . . . . .25
Table 30. Status1Reg register (address 07h); reset value:
Table 31. Description of Status1Reg bits . . . . . . . . . . . . .26
Table 32. Status2Reg register (address 08h); reset value:
Table 33. Description of Status2Reg bits . . . . . . . . . . . . .27
Table 34. FIFODataReg register (address 09h); reset value:
Table 35. Description of FIFODataReg bits . . . . . . . . . . .28
Table 36. FIFOLevelReg register (address 0Ah); reset
Table 37. Description of FIFOLevelReg bits. . . . . . . . . . .28
Table 38. WaterLevelReg register (address 0Bh); reset
Table 39. Description of WaterLevelReg bits . . . . . . . . . .29
Table 40. ControlReg register (address 0Ch); reset value:
PN512
Product data sheet
COMPANY PUBLIC
Quick reference data . . . . . . . . . . . . . . . . . . . . .4
Communication overview for
ISO/IEC 14443 A/MIFARE reader/writer . . . . .10
Communication overview for FeliCa
reader/writer . . . . . . . . . . . . . . . . . . . . . . . . . . .12
FeliCa framing and coding . . . . . . . . . . . . . . . .12
Start value for the CRC Polynomial: (00h), (00h)12
Communication overview for Active
communication mode . . . . . . . . . . . . . . . . . . . .14
communication mode . . . . . . . . . . . . . . . . . . . .15
0000000b . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
value: 20h, 00100000b . . . . . . . . . . . . . . . . . . .20
80h, 10000000b . . . . . . . . . . . . . . . . . . . . . . . .21
00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . .22
14h, 00010100b . . . . . . . . . . . . . . . . . . . . . . . .23
XXh, 000X00XXb . . . . . . . . . . . . . . . . . . . . . . .24
00000000b . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
XXh, X100X01Xb . . . . . . . . . . . . . . . . . . . . . . .26
00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . .27
XXh, XXXXXXXXb . . . . . . . . . . . . . . . . . . . . . .28
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . .28
value: 08h, 00001000b . . . . . . . . . . . . . . . . . . .29
Ordering information . . . . . . . . . . . . . . . . . . . . .4
Pin description HVQFN32 . . . . . . . . . . . . . . . . .8
Pin description HVQFN40 . . . . . . . . . . . . . . . . .9
All information provided in this document is subject to legal disclaimers.
Rev. 3.6 — 10 March 2011
111336
Table 41. Description of ControlReg bits . . . . . . . . . . . . 29
Table 42. BitFramingReg register (address 0Dh); reset
Table 43. Description of BitFramingReg bits . . . . . . . . . . 30
Table 44. CollReg register (address 0Eh); reset value: XXh,
Table 45. Description of CollReg bits. . . . . . . . . . . . . . . . 31
Table 46. PageReg register (address 10h); reset value: 00h,
Table 47. Description of PageReg bits . . . . . . . . . . . . . . 32
Table 48. ModeReg register (address 11h); reset value:
Table 49. Description of ModeReg bits . . . . . . . . . . . . . . 33
Table 50. TxModeReg register (address 12h); reset value:
Table 51. Description of TxModeReg bits . . . . . . . . . . . . 34
Table 52. RxModeReg register (address 13h); reset value:
Table 53. Description of RxModeReg bits . . . . . . . . . . . . 35
Table 54. TxControlReg register (address 14h); reset value:
Table 55. Description of TxControlReg bits . . . . . . . . . . . 36
Table 56. TxAutoReg register (address 15h); reset value:
Table 57. Description of TxAutoReg bits . . . . . . . . . . . . . 37
Table 58. TxSelReg register (address 16h); reset value:
Table 59. Description of TxSelReg bits . . . . . . . . . . . . . . 38
Table 60. RxSelReg register (address 17h); reset value:
Table 61. Description of RxSelReg bits . . . . . . . . . . . . . . 40
Table 62. RxThresholdReg register (address 18h); reset
Table 63. Description of RxThresholdReg bits . . . . . . . . 40
Table 64. DemodReg register (address 19h); reset value:
Table 65. Description of DemodReg bits . . . . . . . . . . . . . 41
Table 66. FelNFC1Reg register (address 1Ah); reset value:
Table 67. Description of FelNFC1Reg bits . . . . . . . . . . . 42
Table 68. FelNFC2Reg register (address1Bh); reset value:
Table 69. Description of FelNFC2Reg bits . . . . . . . . . . . 43
Table 70. MifNFCReg register (address 1Ch); reset value:
Table 71. Description of MifNFCReg bits. . . . . . . . . . . . . 44
Table 72. ManualRCVReg register (address 1Dh); reset
Table 73. Description of ManualRCVReg bits . . . . . . . . . 45
Table 74. TypeBReg register (address 1Eh); reset value:
Table 75. Description of TypeBReg bits. . . . . . . . . . . . . . 46
Table 76. SerialSpeedReg register (address 1Fh); reset
Table 77. Description of SerialSpeedReg bits . . . . . . . . . 47
00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . . 29
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 30
101XXXXXb . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
00000000b . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3Bh, 00111011b . . . . . . . . . . . . . . . . . . . . . . . . 33
00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . . 34
00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . . 35
80h, 10000000b . . . . . . . . . . . . . . . . . . . . . . . . 36
00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . . 37
10h, 00010000b . . . . . . . . . . . . . . . . . . . . . . . . 38
84h, 10000100b . . . . . . . . . . . . . . . . . . . . . . . . 40
value: 84h, 10000100b . . . . . . . . . . . . . . . . . . 40
4Dh, 01001101b. . . . . . . . . . . . . . . . . . . . . . . . 41
00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . . 42
00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . . 43
62h, 01100010b . . . . . . . . . . . . . . . . . . . . . . . . 44
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 45
00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . . 46
value: EBh, 11101011b . . . . . . . . . . . . . . . . . . 46
Transmission module
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PN512
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