PN5120A0HN/C1 NXP Semiconductors, PN5120A0HN/C1 Datasheet - Page 32
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PN5120A0HN/C1
Manufacturer Part Number
PN5120A0HN/C1
Description
Transmission Module 40-Pin HVQFN EP T/R
Manufacturer
NXP Semiconductors
Datasheet
1.PN5120A0HN1C2118.pdf
(125 pages)
Specifications of PN5120A0HN/C1
Package
40HVQFN EP
Operating Temperature
-30 to 85 °C
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PN512
Product data sheet
COMPANY PUBLIC
9.2.2.1 PageReg
9.2.2 Page 1: Communication
Selects the register page.
Table 46.
Table 47.
Bit
7
6 to 2
1 to 0
Access
Rights
Symbol
UsePage Select Set to logic 1, the value of PageSelect is used as register address A5
-
PageSelect
UsePage Select
PageReg register (address 10h); reset value: 00h, 00000000b
Description of PageReg bits
All information provided in this document is subject to legal disclaimers.
r/w
7
Rev. 3.6 — 10 March 2011
Description
and A4. The LSB-bits of the register address are defined by the
address pins or the internal address latch, respectively.
Set to logic 0, the whole content of the internal address latch defines
the register address. The address pins are used as described in
Section 10.1 “Automatic microcontroller interface
Reserved for future use.
The value of PageSelect is used only, if UsePageSelect is set to
logic 1. In this case it specifies the register page (which is A5 and A4
of the register address).
RFU
6
0
111336
RFU
5
0
RFU
4
0
RFU
3
0
RFU
2
0
Transmission module
detection”.
© NXP B.V. 2011. All rights reserved.
r/w
1
PageSelect
PN512
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