PN5120A0HN/C1 NXP Semiconductors, PN5120A0HN/C1 Datasheet - Page 28
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PN5120A0HN/C1
Manufacturer Part Number
PN5120A0HN/C1
Description
Transmission Module 40-Pin HVQFN EP T/R
Manufacturer
NXP Semiconductors
Datasheet
1.PN5120A0HN1C2118.pdf
(125 pages)
Specifications of PN5120A0HN/C1
Package
40HVQFN EP
Operating Temperature
-30 to 85 °C
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PN512
Product data sheet
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9.2.1.10 FIFODataReg
9.2.1.11 FIFOLevelReg
In- and output of 64 byte FIFO-buffer.
Table 34.
Table 35.
Indicates the number of bytes stored in the FIFO.
Table 36.
Table 37.
Bit
7 to 0
Bit
7
6 to 0
Access
Rights
Access
Rights
FlushBuffer
Symbol
FIFOData
Symbol
FlushBuffer
FIFOLevel
FIFODataReg register (address 09h); reset value: XXh, XXXXXXXXb
Description of FIFODataReg bits
FIFOLevelReg register (address 0Ah); reset value: 00h, 00000000b
Description of FIFOLevelReg bits
dy
7
w
7
All information provided in this document is subject to legal disclaimers.
Rev. 3.6 — 10 March 2011
dy
6
Description
Data input and output port for the internal 64 byte FIFO-buffer. The
FIFO-buffer acts as parallel in/parallel out converter for all serial data
stream in- and outputs.
Description
Set to logic 1, this bit clears the internal FIFO-buffer’s read- and
write-pointer and the bit BufferOvfl in the register ErrReg immediately.
Reading this bit will always return 0.
Indicates the number of bytes stored in the FIFO-buffer. Writing to the
FIFODataReg increments, reading decrements the FIFOLevel.
6
r
111336
dy
5
5
r
dy
4
FIFOData
4
r
FIFOLevel
dy
3
3
r
dy
2
2
r
Transmission module
© NXP B.V. 2011. All rights reserved.
dy
1
1
r
PN512
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0
0
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