PN5120A0HN/C1 NXP Semiconductors, PN5120A0HN/C1 Datasheet - Page 24

• Manufacturer Part Number: PN5120A0HN/C1
• Description: Transmission Module 40-Pin HVQFN EP T/R
• Manufacturer: NXP Semiconductors

Specifications of PN5120A0HN/C1

• Package: 40HVQFN EP
• Operating Temperature: -30 to 85 °C

NXP Semiconductors
PN512
Product data sheet
COMPANY PUBLIC
9.2.1.6 DivIRqReg
Contains Interrupt Request bits
Table 26.
Table 27.
All bits in the register DivIRqReg shall be cleared by software.
Bit
7
6 to 5
4
3
2
1
0
Access
Rights
Symbol
Set2
-
SiginActIRq
ModeIRq
CRCIRq
RFOnIRq
RFOffIRq
DivIRqReg register (address 05h); reset value: XXh, 000X00XXb
Description of DivIRqReg bits
Set2
w
7
All information provided in this document is subject to legal disclaimers.
RFU
6
0
Rev. 3.6 — 10 March 2011
Description
Set to logic 1, Set2 defines that the marked bits in the register
DivIRqReg are set.
Set to logic 0, Set2 defines, that the marked bits in the register
DivIRqReg are cleared
Reserved for future use.
Set to logic 1, when SIGIN is active. See
support”. This interrupt is set when either a rising or falling signal edge
is detected.
Set to logic 1, when the mode has been detected by the Data mode
detector.
Note: The Data mode detector can only be activated by the AutoColl
command and is terminated automatically having detected the
Communication mode.
Note: The Data mode detector is automatically restarted after each RF
Reset.
Set to logic 1, when the CRC command is active and all data are
processed.
Set to logic 1, when an external RF field is detected.
Set to logic 1, when a present external RF field is switched off.
RFU
0
5
111336
SiginActIRq ModeIRq
dy
4
dy
3
CRCIRq
dy
Section 12.6 “S
2
Transmission module
RFOnIRq RFOffIRq
© NXP B.V. 2011. All rights reserved.
dy
1
PN512
2
C interface
24 of 125
dy
0