PIC18F65K90-I/MR Microchip Technology, PIC18F65K90-I/MR Datasheet - Page 176

• Manufacturer Part Number: PIC18F65K90-I/MR
• Description: 32kB Flash, 2kB RAM, 1kB EE, NanoWatt XLP, LCD 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F65K90-I/MR

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Timers: 8
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Details

PIC18F87K90 FAMILY
TABLE 11-14: PORTG FUNCTIONS (CONTINUED)
TABLE 11-15: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
DS39957D-page 176
PORTG
TRISG
LCDSE3
ANCON2
ODCON1
ODCON2 CCP10OD
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG.
Note 1:
RG2/RX2/DT2/
AN18/C3INA
RG3/CCP4/AN17/
P3D/C3INB
RG4/SEG26/
RTCC/T7CKI/
T5G/CCP5/
AN16/P1D/
C3INC
RG5
Legend:
Name
Pin Name
2:
This bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented.
Unimplemented in devices with a program memory of 32 Kbytes (PIC18FX5K90).
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
ANSEL23 ANSEL22 ANSEL21 ANSEL20 ANSEL19 ANSEL18 ANSEL17 ANSEL16
SSP1OD
SE31
Bit 7
—
—
Function
SEG26
C3INA
C3INB
C3INC
T7CKI
CCP4
RTCC
CCP5
AN18
AN17
AN16
RG2
RG3
RG4
RX2
DT2
P3D
T5G
P1D
(2)
CCP9OD
CCP2OD CCP1OD
SE30
Bit 6
—
—
Setting
TRIS
0
1
1
1
1
1
x
0
1
0
1
1
x
0
0
1
1
x
x
x
0
1
1
x
0
(2)
CCP8OD CCP7OD CCP6OD CCP5OD CCP4OD CCP3OD
RG5
SE29
Bit 5
—
I/O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
(1)
Type
ANA
ANA
ANA
ANA
ANA
ANA
ANA
DIG
DIG
DIG
DIG
DIG
DIG
DIG
TRISG4
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
—
—
SE28
Bit 4
RG4
—
LATG<2> data output.
PORTG<2> data input.
Asynchronous serial receive data input (EUSART module).
Synchronous serial data output (EUSART module); takes priority over
port data.
Synchronous serial data input (EUSART module); user must configure
as an input.
A/D Input Channel 18. Default input configuration on POR; does not
affect digital output.
Comparator 3 Input A.
LATG<3> data output.
PORTG<3> data input.
CCP4 compare/PWM output; takes priority over port data.
CCP4 capture input.
A/D Input Channel 17. Default input configuration on PR; does not
affect digital output.
Comparator 3 Input B.
ECCP3 PWM Output D. May be configured for tri-state during
Enhanced PWM.
LATG<4> data output.
PORTG<4> data input.
LCD Segment 26 output; disables all other pin functions.
RTCC output.
Timer7 clock input.
Timer5 external clock gate input.
CCP5 compare/PWM output; takes priority over port data.
CCP5 capture input.
A/D Input Channel 17. Default input configuration on POR; does not
affect digital output.
Comparator 3 Input C.
ECCP1 PWM Output D. May be configured for tri-state during
Enhanced PWM.
See the MCLR/RG5 pin.
TRISG3
SE27
Bit 3
RG3
—
TRISG2
SE26
Bit 2
RG2
—
Description
TRISG1
 2009-2011 Microchip Technology Inc.
SE25
Bit 1
RG1
—
SSP2OD
TRISG0
SE24
Bit 0
RG0
Reset Values
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