ZPSD511B1C15J STMicroelectronics, ZPSD511B1C15J Datasheet - Page 91

• Manufacturer Part Number: ZPSD511B1C15J
• Manufacturer: STMicroelectronics

Specifications of ZPSD511B1C15J

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Counter/Timer
Registers
(Cont.)
88
PSD5XX Family
9.6.2.5 Software Load/Store Register:
Each bit in this register enables a load to the corresponding Counter/Timer from its
associated Image Register in Waveform, Pulse or WatchDog modes. The actual counts
are stored in their corresponding Image Register in event Counter or time capture modes.
Bit 6 of the Command Register must be set to “1” before writing to the software load/store
register.
NOTE:
Software Load/Store 0 Bit: If this bit is set to
Software Load/Store 1 Bit: If this bit is set to
Software Load/Store 2 Bit: If this bit is set to
Software Load/Store 3 Bit: If this bit is set to
**
The Software load/store bits are automatically cleared by the served Counter.
In addition to four CTU registers, there are delay cycle and Counter/Timer status registers.
These are summarized on the following pages.
Bit 7
Load operation takes place in Waveform, Pulse and WatchDog mode.
Store operation takes place in Event Count and Time Capture mode.
*
*
= Not used.
Bit 6
*
Bit 5
*
Bit 4
*
1: Counter/Timer0 CNTR0 gets loaded from the Image
Register IMG0 or CNTR0 stores into IMG0 based on the
mode of operation
1: Counter/Timer1 CNTR1 gets loaded from the Image
Register IMG1 or CNTR1 stores into IMG1 based on the
mode of operation
1: Counter/Timer2 CNTR2 gets loaded from the Image
Register IMG2.
1: Counter/Timer3 CNTR3 gets loaded from the Image
Register IMG3 or CNTR3 stores into IMG3 based on the
mode of operation
Software
Load/Store 3 Load/Store 2 Load/Store 1 Load/Store 0
Bit 3
**
**
**
Software
.
.
.
Bit 2
Software
Bit 1
Software
Bit 0