ZPSD511B1C15J STMicroelectronics, ZPSD511B1C15J Datasheet - Page 101

• Manufacturer Part Number: ZPSD511B1C15J
• Manufacturer: STMicroelectronics

Specifications of ZPSD511B1C15J

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Interrupt
Controller
(Cont.)
98
PSD5XX Family
Table 29a. Offset Address Map of Interrupt Registers
(For 16-Bit Motorola MCUs in 16-Bit Mode. If 8-Bit Mode is selected, use Table 29.)
Table 29. Offset Address Map of Interrupt Registers
Interrupt Mask Register
Interrupt Operation
9.7.1.1 Command Registers
All the eight interrupts can be individually masked using a mask register. Writing “ones”
into these mask bits enables the associated interrupts. RESET masks all interrupts.
Interrupts can also be defined as either LEVEL sensitive or EDGE sensitive using a
sensitivity bit in the interrupt edge/level sensitivity select register.
Tables 29 and 29a give the address map for various port and interrupt Command/Status
Registers. This address offset map is of the host processor, relative to the CSIOP
(Chip Select Input Output Port) i.e., address space allocated by the host Microcontroller to
access all the PSD embedded peripherals.
The Interrupt Registers listed in Tables 29 and 29a are described below.
Bits mask 0
When these bits are set to
1 = Unmasked
0 = Masked
At RESET these bits initialize as 0 and all interrupts are masked.
Mask7
Bit 7
Address
Address
Offset
Offset
+D3h
+D1h
+D2h
+D0h
...
Mask6
mask 7 correspond to interrupt 0
Bit 6
Interrupt Mask
Interrupt Request Latch
Interrupt Mask
Interrupt Request Latch
Register Name
Register Name
(Cont.)
Mask5
Bit 5
Mask4
Bit 4
...
Mask3
Bit 3
Address
Address
interrupt 7.
Offset
Offset
+D4h
+D2h
+D0h
+D5h
+D3h
+D1h
Mask2
Bit 2
Interrupt Read Clear
Interrupt Edge/Level
Select
Interrupt Priority Status
Interrupt Read Clear
Interrupt Edge/Level
Select
Interrupt Priority Status
Register Name
Register Name
Mask1
Bit 1
Mask0
Bit 0