ZPSD511B1C15J STMicroelectronics, ZPSD511B1C15J Datasheet - Page 110

• Manufacturer Part Number: ZPSD511B1C15J
• Manufacturer: STMicroelectronics

Specifications of ZPSD511B1C15J

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

System
Configuration
(Cont.)
Table 33. Other Register Function
PAGE REGISTER
INTR. READ
CLEAR
INTR.
EDGE/LEVEL
INTR. MASK
INTR.
REQUEST LATCH
INTR.
PRIORITY STATUS
VM
PMMR0
PMMR1
STATUS FLAGS
GLOBAL
COMMAND
DLCY
SOFTWARE
LOAD/STORE
FREEZE
COMMAND
CMD3 – 0
CNTR3 – 0
IMG3 – 0
Register Name
A 4-bit register that supports paging.
Reading this register clears all the pending edge sensitive
interrupts.
Define interrupt input as level or edge sensitive.
Mask selected interrupt input.
A “1” in the register indicates the corresponding interrupt is
pending.
The register indicates which pending interrupt has the highest
priority.
1. Configures the PSD SRAM to be accessed by “PSEN” as
2. Enable the Peripheral I/O Mode of Port A.
Power management registers; enable the PSD Power Down Mode
and other power saving configurations.
Counter/Timer Freeze Acknowledge bits.
Specifies the Counter/Timer operation mode; and to start or stop
the Counter/Timers.
Specifies the delay cycles to the Counter/Timers.
This register enables a load (to the Counter/Timer) or store
(in the Image Register) operation.
This register disables the timer state-machine before access to the
Image Register is allowed.
Command Registers for the configuration of the Counter/Timers.
The four 16-bit Counter/Timers.
The Image Registers for CNTR3 – 0.
program space (8031 design).
Register Function
PSD5XX Family
107