ZPSD511B1C15J STMicroelectronics, ZPSD511B1C15J Datasheet - Page 88

• Manufacturer Part Number: ZPSD511B1C15J
• Manufacturer: STMicroelectronics

Specifications of ZPSD511B1C15J

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Counter/Timer
Registers
(Cont.)
Command Registers for Counter/Timers CMD0, CMD1, CMD2, CMD3 (Cont.)
Output Polarity Bit (3):
Input Polarity Bit (4):
Pin / PPLD Macrocell Bit (5): This bit determines whether the Counter/Timer0 gets its
Software Gating Bit for
Load/Store Commands (6):
Enable/Disable Using PIN,
PPLD Macrocell or Software command is activated by the PSD5XX Pin, PPLD macrocell
Bit (7):
This bit is valid only in Waveform or Pulse mode and is
used to select the polarity of the Active output signal
of the Counter/Timer0. At RESET this bit initializes as 0
which means the Active output state is LOW. When this bit
is set to a
1: The Active output state is HIGH.
0: The Active output state is LOW.
The state of this bit determines the polarity of the Active
input control signal to the Counter/Timer0 and is valid only
for input pin. At RESET this bit initializes as 0 which means
that the input Active is HIGH. When this bit is set to a
1: The input Active is LOW.
0: The input Active is HIGH.
input command for Load/Store and Enable/Disable from
the PSD5XX PIN or from the PPLD macrocell output.
At RESET this bit initializes as 0 which means that the
input command is coming from the PSD5XX PPLD
macrocell. When this bit is set to a
1: The Counter/Timer0 input command is coming from
0: The Counter/Timer0 input command is coming
This bit gates the Load/Store command activated by the
PSD5XX PIN or PPLD macrocell. At RESET this bit
initializes as 0 which means that the Load/Store command
activated by the PIN or macrocell is permitted through.
When this bit is set to
1: Load/Store operation activated by PIN or Macrocell is
0: Load/Store operation activated by PIN or macrocell is
This bit determines whether the Enable/Disable
or by Software. At RESET this bit initializes as 0, which
means that the Enable/Disable command is activated by
the PIN or PPLD macrocell. When this bit is set to
1: Enable/Disable command by PIN or macrocell is
0: Enable/Disable command is activated by PIN or
the PIN.
from the PPLD macrocell output.
NOT permitted through.
permitted through. To further decide between the PIN
and PPLD macrocell, use bit 5 (PIN/PPLD macrocell).
overridden by Software (only Bit 2 of this register will
enable or disable the counter).
Macrocell output. To further decide between the PIN and
PPLD macrocell use bit 5 (PIN / PPLD macrocell bit).
PSD5XX Family
85