ZPSD511B1C15J STMicroelectronics, ZPSD511B1C15J Datasheet - Page 102

• Manufacturer Part Number: ZPSD511B1C15J
• Manufacturer: STMicroelectronics

Specifications of ZPSD511B1C15J

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Interrupt
Controller
(Cont.)
Interrupt Operation
Interrupt Edge/Level Select Register
Interrupt Request Latch Register
Interrupt Priority Status Register
Interrupt Read Clear Register
NOTE:
Bits sense 0
When these bits are set to
1 = LEVEL sensitive
0 = EDGE sensitive (positive edge)
At RESET these bits initialize as 0 i.e., all interrupts come up as Edge sensitive.
This is a read only register. Reading this register during initialization clears all the pending
edge sensitive interrupts.
Bits ir 0...ir 7 correspond to interrupt 0 ... interrupt 7.
When any of these bits are set by the interrupt controller to a “1”, the corresponding
Interrupt is pending service.
The MCU can read the interrupt request latch which shows the status of all interrupts. The
entire interrupt request latch can be cleared by reading the Interrupt Read Clear Register,
but Level sensitive interrupts cannot be cleared.
The value of these 3 bits (vect2, vect1 and vect0) indicates the highest priority of the
interrupt to be serviced among multiple interrupts pending. Refer to the table above for
priorities of various interrupts. Reading this register clears the highest pending interrupt.
Sense7
Bit 7
Bit 7
Bit 7
ir 7
*
*
= Reserved for future use, bits set to zero.
...
Sense6
Bit 6
Bit 6
Bit 6
sense 7 correspond to interrupt 0
ir 6
*
(cont.)
Sense5
Bit 5
Bit 5
Bit 5
ir 5
*
Sense4
Bit 4
Bit 4
Bit 4
ir 4
*
Sense3
...
Bit 3
Bit 3
Bit 3
ir 3
*
interrupt 7.
Sense2
vect 2
Bit 2
Bit 2
Bit 2
ir 2
Sense1
vect 1
Bit 1
Bit 1
Bit 1
ir 1
PSD5XX Family
Sense0
vect 0
Bit 0
Bit 0
Bit 0
ir 0
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