ZPSD511B1C15J STMicroelectronics, ZPSD511B1C15J Datasheet - Page 55

• Manufacturer Part Number: ZPSD511B1C15J
• Manufacturer: STMicroelectronics

Specifications of ZPSD511B1C15J

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

9.4
Memory
Block
52
PSD5XX Family
The PSD5XX provides EPROM memory for code storage and SRAM memory for scratch
pad usage. Chip selects for the memory blocks come from the DPLD decoding logic and are
defined by the user in the PSDsoft Software. Figure 26 shows the organization of the
Memory Block.
All PSD families use Zero-power memory techniques that place memory into standby
between MCU accesses. The memory becomes active briefly after an address transition,
then delivers new data to the outputs, latches the outputs, and returns to standby. This is
done automatically and the designer has to do nothing special to benefit from this feature.
9.4.1 EPROM
The PSD5XX provides three EPROM densities: 256Kbit, 512Kbit or 1Mbit. The EPROM
is divided into four 8K, 16K or 32K byte blocks. Each block has its own chip select signals
(ES0 – ES3). The EPROM can be configured as 32K x 8, 64K x 8 or 128K x 8 for
microcontrollers with an 8-bit data bus. For 16-bit data buses, the EPROM is configured as
16K x 16, 32K x 16, or 64K x 16.
9.4.2 SRAM
The SRAM has 16Kbits of memory, organized as 2K x 8 or 1K x 16. The SRAM is enabled
by the chip select signal RS0 from the DPLD. The SRAM has a battery back-up (STBY)
mode. This back-up mode is invoked when the V
by 0.6 V. The VSTBY voltage is connected only to the SRAM and cannot be lower than
2.7 volts. The SRAM Data Retention voltage is 2 volts.
9.4.3 Memory Select Map
The EPROM and SRAM chip select equations are defined in the ABEL file in terms of
address and other DPLD inputs. The memory space for the EPROM chip select
(ES0 – ES3) should not be larger than the EPROM block (8KB, 16KB or 32KB) it is
selecting.
The following rules govern how the internal PSD5XX memory selects/space are defined:
The Peripheral I/O space refers to memory space occupied by peripherals when Port A is
configured in the Peripheral I/O Mode.
The EPROM blocks address space cannot overlap
SRAM, internal I/O and Peripheral I/O space cannot overlap
SRAM, internal I/O and Peripheral I/O space can overlap EPROM space, with priority
given to SRAM or I/O. The portion of EPROM which is overlapped cannot be accessed.
CC
voltage drops under the VSTBY voltage