ZPSD511B1C15J STMicroelectronics, ZPSD511B1C15J Datasheet - Page 65

• Manufacturer Part Number: ZPSD511B1C15J
• Manufacturer: STMicroelectronics

Specifications of ZPSD511B1C15J

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Power
Management
Unit
(Cont.)
62
PSD5XX Family
Summary of PSD5XX Timing and Standby Current During Power Down
and Sleep Modes
The Counter/Timers can operate in Sleep Mode if the TMR CLK bit is low, but the power
consumption will be based on the frequency of operation (CLKIN frequency).
Table 20. I/O Pin Status During Power Down And Sleep Mode
NOTES: 1. Power Down does not affect the operation of the ZPLD. The ZPLD operation in this mode is based
Power Down
Sleep
Input Clock
The PSD5XX provides the option to turn off the clock inputs to save AC power
consumption. The clock input (CLKIN) is used as a source for driving the following
modules:
ZPLD Array Clock Input
ZPLD MacroCell Clock Flip Flop
APD Counter Clock
Counter/Timers Clock
During power down or if any of the modules are not being used the clock to these
modules should be disabled. To reduce AC power consumption, it is especially important
to disable the clock input to the ZPLDS array if it is not used as part of a logic equation.
The ZPLD Array Clock can be disabled by setting PMMR0 bit 5 (ZPLD ACLK). The ZPLD
MacroCell Clock Input can be disabled by setting PMMR0 bit 6 (ZPLD RCLK). The Timer
Clock can be disabled by setting PMMR0 bit 7 (TMR CLK). The APD Counter Clock
will be disabled automatically if Power Down or Sleep Mode is entered through the APD
unit. The input buffer of the CLKIN input will be disabled if bits 5 – 7 PMMR0 are set and
the APD has overflowed.
2. In Sleep Mode any input to the ZPLD will have a propagation delay of t
3. PLD recovery time to normal operation after exiting Sleep Mode. An input to the ZPLD during the
only on the ZPLD_Turbo Bit.
transition will have a propagation delay time of t
I/O Port
ZPLD Output
Address Out
Data Port
Special Function Out
Peripheral I/O
Port Configuration
Propagation
Normal t
(Note 1)
(Note 2)
Delay
t
PLD
LVDV2
PD
Operation
Recovery
Time To
Normal
(Note 3)
t
PLD
LVDV3
0
LVDV3
Unchanged
Depend on Inputs to the ZPLD
Undefined
Tri-stated
Depending on Status of Clock Input
Tri-stated
.
No Access
No Access
Access
Time
Pin Status
LVDV2
.
Recovery
Time To
Normal
Access
Access
t
t
LVDV1
LVDV