ZPSD511B1C15J STMicroelectronics, ZPSD511B1C15J Datasheet - Page 84

• Manufacturer Part Number: ZPSD511B1C15J
• Manufacturer: STMicroelectronics

Specifications of ZPSD511B1C15J

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Counter/Timer
Operation
(Cont.)
Table 23. Offset Address Map of Counter/Timer-Unit Registers
9.6.2 Counter/Timer Registers
Registers CNTR0,CNTR1,CNTR2 and CNTR3 serve as actual counting logic. Registers
IMG0,IMG1,IMG2 and IMG3 serve as images of these Counter/Timers. Depending upon the
selected mode of operation, a Counter can load a new value or transfer its content to the
image register. Registers IMG0 - IMG3 and CNTR0 - CNTR3 are accessible to the
Microcontroller only before setting the start bit (Bit 1 in the Global Command Register).
When CNTR0-CNTR3 are active, the value in the read operation is not guaranteed to be
stable and during a write operation there could be contention between the image register
write and microcontroller write. Therefore the access of registers CNTR0-CNTR3 should
be suspended when the Counter/Timers are active. Only IMG0, IMG1, IMG2 and IMG3
registers are accessible when the Counter/Timers are active.
Tables 23 and 23a give the address map for the various port and Counter/Timer-unit
registers. This address offset map is of the host processor, relative to CSIOP (Chip Select
Input Output Port) i.e. address space allocated by the host Microcontroller to access all the
PSD5XX embedded peripherals.
Table 23a is for 16-bit Motorola Microcontrollers which require different address offsets.
Address
Offset
+A9h
+A5h
+A3h
+A1h
+9Dh
+9Bh
+9Fh
+99h
+97h
+95h
+93h
+91h
STATUS FLAGS
SOFTWARE LOAD/STORE
CMD3
CMD1
CNTR3
CNTR2
CNTR1
CNTR0
IMG3
IMG2
IMG1
IMG0
Register Name
Address
Offset
+A8h
+A6h
+A4h
+A2h
+A0h
+9Eh
+9Ch
+9Ah
+98h
+96h
+94h
+92h
+90h
GLOBAL COMMAND
DLCY
FREEZE COMMAND
CMD2
CMD0
CNTR3
CNTR2
CNTR1
CNTR0
IMG3
IMG2
IMG1
IMG0
Register Name
PSD5XX Family
81