JS28F512P33BFD Micron Technology Inc, JS28F512P33BFD Datasheet - Page 56

• Manufacturer Part Number: JS28F512P33BFD
• Manufacturer: Micron Technology Inc

Specifications of JS28F512P33BFD

• Cell Type: NOR
• Density: 512Mb
• Access Time (max): 105/17ns
• Interface Type: Parallel/Serial
• Boot Type: Bottom
• Address Bus: 25b
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 8.5 to 9.5V
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 32M
• Supply Current: 31mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 26: AC Write Specifications (Sheet 2 of 2)
Figure 24: Write-to-Write Timing
Datasheet
58
Write to Synchronous Read Specifications
W19
W20
W28
Write Specifications with Clock Active
W21
W22
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
Num
Address [A]
Data [D/Q]
RST# [P]
WE# [W]
OE# [G]
CE# [E]
Write timing characteristics during erase suspend are the same as write-only operations.
A write operation can be terminated with either CE# or WE#.
Sampled, not 100% tested.
Write pulse width low (t
(whichever occurs first). Hence, t
Write pulse width high (t
(whichever occurs last). Hence, t
t
VPP and WP# should be at a valid level until erase or program success is determined.
This specification is only applicable when transiting from a write cycle to an asynchronous read. See spec W19 and W20
for synchronous read.
When doing a Read Status operation following any command that alters the Status Register, W14 is 20ns.
Add 10ns if the write operations results in a RCR or block lock status change, for the subsequent read operation to
reflect this change.
These specs are required only when the device is in a synchronous mode and clock is active during address setup phase.
These specs are required only when ADV# is used to latch address.
This specification must be complied with by customer’s writing timing. The result would be unpredictable if any violation
to this timing specification.
WHVH
t
t
t
t
t
WHCH/L
WHVH
WHVL
VHWL
CHWL
Symbol
or t
WHCH/L
W1
WE# high to Clock valid
WE# high to ADV# high
WE# high to ADV# low
ADV# high to WE# low
Clock high to WE# low
W2
must be met when transiting from a write cycle to a synchronous burst read.
WLWH
WHWL
or t
W5
or t
ELEH
WHWL
WLWH
EHEL
W3
W3
Parameter
) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high
) is defined from CE# or WE# high (whichever occurs first) to CE# or WE# low
= t
= t
W4
EHEL
ELEH
= t
= t
WHEL
WLEH
W7
W6
= t
= t
W8
EHWL
ELWH
W9
W9
).
.
W2
Min
19
19
7
-
-
W5
W3
W3
W4
Max
20
20
-
-
-
Order Number: 208043-05
Unit
ns
ns
ns
ns
ns
W7
W6
W8
1,2,3,6,10
1,2,3,11.1
P33-65nm
Notes
Apr 2010
,12
2