JS28F512P33BFD Micron Technology Inc, JS28F512P33BFD Datasheet - Page 14

• Manufacturer Part Number: JS28F512P33BFD
• Manufacturer: Micron Technology Inc

Specifications of JS28F512P33BFD

• Cell Type: NOR
• Density: 512Mb
• Access Time (max): 105/17ns
• Interface Type: Parallel/Serial
• Boot Type: Bottom
• Address Bus: 25b
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 8.5 to 9.5V
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 32M
• Supply Current: 31mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Supplier Unconfirmed

4.0
Table 4:
Datasheet
16
A[MAX:1]
DQ[15:0]
ADV#
CE#
CLK
OE#
RST#
WAIT
WE#
WP#
VPP
VCC
VCCQ
VSS
Symbol
TSOP and Easy BGA Signal Descriptions (Sheet 1 of 2)
Signals
Output
Output
Power/
Input/
Power
Power
Power
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
ADDRESS INPUTS: Device address inputs. 512-Mbit: A[25:1], 1-Gbit: A[26:1], 2-Gbit: A[27:1].
Note: The virtual selection of the upper 1-Gbit die in the dual-die 2-Gbit configuration is
accomplished by setting A27 high (V
DATA INPUT/OUTPUTS: Inputs data and commands during write cycles; outputs data during
reads of memory, Status Register, OTP Register, and Read Configuration Register. Data balls/pins
float when the CE# or OE# are deasserted. Data is internally latched during writes.
ADDRESS VALID: Active low input.
Easy BGA: During synchronous read operations, addresses are latched on the rising edge of ADV#,
or on the next valid CLK edge with ADV# low, whichever occurs first. In asynchronous mode, ADV#
can be either driven high to latch the address or held low throught the read cycle.
TSOP: ADV# must be tied to VSS or held low throughout the read cycle.
WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through.
CHIP ENABLE: Active low input. CE# low selects the associated flash memory die. When asserted,
flash internal control logic, input buffers, decoders, and sense amplifiers are active. When
deasserted, the associated flash die is deselected, power is reduced to standby levels, data and
WAIT outputs are placed in high-Z state.
WARNING: Chip Enable must be high when device is not in use.
CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode.
During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the
next valid CLK edge with ADV# low, whichever occurs first.
WARNING: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS.
OUTPUT ENABLE: Active low input. OE# low enables the device’s output data buffers during read
cycles. OE# high places the data outputs and WAIT in High-Z.
RESET: Active low input. RST# resets internal automation and inhibits write operations. This
provides data protection during power transitions. RST# high enables normal operation. Exit from
reset places the device in asynchronous read array mode.
WAIT: Indicates data valid in synchronous array or non-array burst reads. RCR.10, (WT) determines
its polarity when asserted. WAIT’s active output is V
high-Z if CE# or OE# is V
WRITE ENABLE: Active low input. WE# controls writes to the device. Address and data are latched
on the rising edge of WE#.
WRITE PROTECT: Active low input. WP# low enables the lock-down mechanism. Blocks in lock-
down cannot be unlocked with the Unlock command. WP# high overrides the lock-down function
enabling blocks to be erased or programmed using software commands.
ERASE AND PROGRAM POWER: A valid voltage on this pin allows erasing or programming.
Memory contents cannot be altered when VPP ≤ V
voltages should not be attempted.
Set VPP = V
from the system supply, the V
min to perform in-system flash modification. VPP may be 0 V during read operations.
V
cumulative total not to exceed 80 hours. Extended use of this pin at 9 V may reduce block cycling
capability.
DEVICE CORE POWER SUPPLY: Core (logic) source voltage. Writes to the flash array are inhibited
when VCC ≤ V
OUTPUT POWER SUPPLY: Output-driver source voltage.
GROUND: Connect to system ground. Do not float any VSS connection.
• In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and
• In asynchronous page mode, and all write modes, WAIT is deasserted.
PPH
valid data when deasserted.
can be applied to array blocks for 1000 cycles maximum. VPP can be connected to 9 V for a
PPL
LKO
for in-system program and erase operations. To accommodate resistor or diode drops
. Operations at invalid VCC voltages should not be attempted.
IH
.
IH
level of VPP can be as low as V
IH
).
Name and Function
PPLK
OL
. Block erase and program at invalid VPP
or V
OH
when CE# and OE# are V
PPL
min. VPP must remain above V
Order Number: 208043-05
IL
. WAIT is
P33-65nm
Apr 2010
PPL