JS28F512P33BFD Micron Technology Inc, JS28F512P33BFD Datasheet - Page 18

• Manufacturer Part Number: JS28F512P33BFD
• Manufacturer: Micron Technology Inc

Specifications of JS28F512P33BFD

• Cell Type: NOR
• Density: 512Mb
• Access Time (max): 105/17ns
• Interface Type: Parallel/Serial
• Boot Type: Bottom
• Address Bus: 25b
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 8.5 to 9.5V
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 32M
• Supply Current: 31mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Supplier Unconfirmed

5.5
5.6
5.7
Datasheet
20
Output Disable
When OE# is deasserted, device outputs DQ[15:0] are disabled and placed in a high-
impedance (High-Z) state, WAIT is also placed in High-Z.
Standby
When CE# is deasserted the device is deselected and placed in standby, substantially
reducing power consumption. In standby, the data outputs are placed in High-Z,
independent of the level placed on OE#. Standby current, I
measured over any 5 ms time interval, 5 μs after CE# is deasserted.
When the device is deselected (while CE# is deasserted) during a program or erase
operation, it continues to consume active power until the program or erase operation is
completed.
Reset
As with any automated device, it is important to assert RST# when the system is reset.
When the system comes out of reset, the system processor attempts to read from the
flash memory if it is the system boot device. If a CPU reset occurs with no flash
memory reset, improper CPU initialization may occur because the flash memory may
be providing status information rather than array data. Flash memory devices from
Numonyx allow proper CPU initialization following a system reset through the use of the
RST# input.
After initial power-up or reset, the device defaults to asynchronous Read Array mode,
and the Status Register is set to 0x80.
When RST# is driven low (RST# asserted), the flash device enters reset mode. Then all
internal circuits are de-energized, and the output drivers are placed in High-Z. If RST#
is asserted during a program or erase operation, the operation is terminated and the
memory contents at the aborted location (for a program) or block (for an erase) are no
longer valid. A device reset also clears the Status Register. See
Reset” on page 46
When RST# is driven high (RST# deasserted), a minimum wait is required before the
flash device is able to perform normal operations. Please consider t
(W1) during system design. see
Section 26, “AC Write Specifications” on page
normal operation is ready for execution.
for RST# timing detail.
Table 25, “AC Read Specifications -” on page
57. After this wake-up interval passes,
CCS
, is the average current
Table 18, “Power and
Order Number: 208043-05
PHQV
(R5) and t
53. and
P33-65nm
Apr 2010
PHWL