JS28F512P33BFD Micron Technology Inc, JS28F512P33BFD Datasheet - Page 23

• Manufacturer Part Number: JS28F512P33BFD
• Manufacturer: Micron Technology Inc

Specifications of JS28F512P33BFD

• Cell Type: NOR
• Density: 512Mb
• Access Time (max): 105/17ns
• Interface Type: Parallel/Serial
• Boot Type: Bottom
• Address Bus: 25b
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 8.5 to 9.5V
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 32M
• Supply Current: 31mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Supplier Unconfirmed

P33-65nm
Table 8:
Table 9:
7.3
7.4
7.5
Datasheet
25
Lock Register 1
128-bit User-Programmable OTP registers
Notes:
1.
2.
3.
Note:
ID Code Type
Device Code
BBA = Block Base Address.
DBA = Device base Address, Numonyx reserves other configuration address locations.
In P33-65nm, the GPR is used as read out register for Extended Function Interface command.
The 2-Gbit devices do not have a unique Device ID associated with them. Each die within the stack can be identified by
the ID codes.
Device Identifier Information (Sheet 2 of 2)
Device ID codes
Read CFI
The Read CFI command instructs the device to output Common Flash Interface data
when read. See
information.
Read Status Register
To read the Status Register, issue the Read Status Register command at any address.
Status Register information is available to which the Read Status Register, Word
Program, or Block Erase command was issued. SRD is automatically made available
following a Word Program, Block Erase, or Block Lock command sequence. Reads from
the device after any of these command sequences outputs the device’s status until
another valid command is written (e.g. the Read Array command).
The Status Register is read using single asynchronous-mode or synchronous burst
mode reads. SRD is output on DQ[7:0], while 0x00 is output on DQ[15:8]. In
asynchronous mode the falling edge of OE#, or CE# (whichever occurs first) updates
and latches the Status Register contents. However, when reading the Status Register in
synchronous burst mode, CE# or ADV# must be toggled to update SRD.
The Device Write Status bit (SR.7) provides overall status of the device. SR[6:1]
present status and error information about the program, erase, suspend, VPP, and
block-locked operations.
See
Register.
Clear Status Register
The Clear Status Register command clears the Status Register. It functions independent
of VPP. The WSM sets and clears SR.7, but it sets bits SR[5:3,1] without clearing them.
The Status Register should be cleared before starting a command sequence to avoid
any ambiguity. A device reset also clears the Status Register.
Device Density
Table 12, “Status Register Description” on page 36
512-Mbit
Item
1-Gbit
Section A.1, “Common Flash Interface” on page 63
(Top Parameter)
8964
8966
-T
Address
0x8A–0x109
0x89
Device Identifier Codes
(Bottom Parameter)
(1,2)
8965
8967
-B
for the description of the Status
User OTP Register data
OTP Register lock data
(Symmetrical Blocks)
Data(x16)
Order Number:208043-05
for detailed
899E
899F
-E
Apr 2010