JS28F512P33BFD Micron Technology Inc, JS28F512P33BFD Datasheet
JS28F512P33BFD
Specifications of JS28F512P33BFD
Available stocks
Related parts for JS28F512P33BFD
JS28F512P33BFD Summary of contents
Page 1
... Numonyx Flash Data Integrator optimized — Basic Command Set and Extended Function Interface (EFI) Command Set compatible — Common Flash Interface capable Density and Packaging — 56-Lead TSOP(512-Mbit, 1-Gbit) — 64-Ball Easy BGA(512-Mbit, 1-Gbit, 2-Gbit) — 16-bit wide data bus Quality and Reliability — ...
Page 2
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR Legal Lines and Disclaimers OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS ...
Page 3
P33-65nm Contents 1.0 Functional Description ............................................................................................... 7 1.1 Introduction ....................................................................................................... 7 1.2 Overview ........................................................................................................... 7 1.3 Virtual Chip Enable Description (2-Gbit) ................................................................. 8 1.4 Memory Map....................................................................................................... 9 2.0 Package Information ............................................................................................... 11 2.1 56-Lead TSOP Package (512-Mbit, 1-Gbit) ............................................................ 11 ...
Page 4
... Capacitance ......................................................................................................52 15.3 AC Read Specifications ......................................................................................53 15.4 AC Write Specifications .......................................................................................57 15.5 Program and Erase Characteristics .......................................................................61 16.0 Ordering Information...............................................................................................62 A Supplemental Reference Information.......................................................................63 A.1 Common Flash Interface .....................................................................................63 A.2 Flowcharts ........................................................................................................74 A.3 Write State Machine ...........................................................................................83 B Conventions - Additional Documentation .................................................................87 B.1 Acronyms .........................................................................................................87 B.2 Definitions and Terms ........................................................................................87 C Revision History.......................................................................................................88 ...
Page 5
... Program Suspend allows system software to pause programming to read other locations. The P33-65nm OTP Register allows unique flash device identification that can be used to increase system security. The individual Block Lock feature provides zero-latency block locking and unlocking. The P33-65nm device adds enhanced protection via Password Access ...
Page 6
... CE# asserted. When chip enable is asserted and A27 is low ( lower die is selected; when chip enable is asserted and A27 is high ( is selected. Table 1: Flash Die Virtual Chip Enable Truth Table for 2-Gbit (1-Gbit/1-Gbit) Devices Die Selected Lower Die Upper Die ...
Page 7
P33-65nm 1.4 Memory Map Figure 1: P33-65nm Memory Map (512-Mbit and 1-Gbit Densities) 3FF0000 -3FFFFFF 64 - Kword Block 64 - Kword Block 1FF0000 -1FFFFFF 64 - Kword Block FF0000 -FFFFFF 64 - Kword Block 020000 -02FFFF 64 - Kword ...
Page 8
Figure 2: P33-65nm Memory Map (2-Gbit) 7FF0000 -7FFFFFF 4010000 -401FFFF 4000000 -400FFFF 3FF0000 -3FFFFFF 1FF0000 -1FFFFFF FF0000-FFFFFF 020000 -02FFFF 010000 -01FFFF 000000 -00FFFF Datasheet 27:1 ] 2-Gbit (1-Gbit/1-Gbit) 64- Kword Block 64- Kword Block 64- Kword Block ...
Page 9
P33-65nm 2.0 Package Information 2.1 56-Lead TSOP Package (512-Mbit, 1-Gbit) Figure 3: TSOP Mechanical Specifications Z See Notes 1 and 3 Pin 1 See Detail A Detail A Table 2: TSOP Package Dimensions (Sheet Product Information Symbol ...
Page 10
Table 2: TSOP Package Dimensions (Sheet Product Information Symbol Lead Count N Lead Tip Angle θ Seating Plane Coplanarity Y Lead to Package Offset Z Notes: 1. One dimple on package denotes Pin two ...
Page 11
P33-65nm Table 3: Easy BGA Package Dimensions for 8x10x1.2 mm (Sheet Product Information Package Body Length Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along D Corner to Ball A1 Distance Along E ...
Page 12
... A25 is valid for 512-Mbit densities and above; otherwise connect (NC). 4. A26 is valid for 1-Gbit density and above; otherwise connect (NC). 5. One dimple on package denotes Pin 1 which will always be in the upper left corner of the package, in reference to the product mark. Datasheet 14 Flash Memory 56-Lead TSOP Pinout Top View P33-65nm 56 WAIT 55 ...
Page 13
P33-65nm Figure 6: 64-Ball Easy BGA Ballout (512-Mbit, 1-Gbit, 2-Gbit VPP B A2 VSS A9 CE A10 A12 A11 RST# VCCQ E DQ8 DQ1 DQ9 DQ3 ...
Page 14
... VPP can be connected for a PPH cumulative total not to exceed 80 hours. Extended use of this pin may reduce block cycling capability. DEVICE CORE POWER SUPPLY: Core (logic) source voltage. Writes to the flash array are inhibited VCC Power when VCC ≤ V ...
Page 15
P33-65nm Table 4: TSOP and Easy BGA Signal Descriptions (Sheet Symbol Type RESERVED FOR FUTURE USE: Reserved by Numonyx for future device functionality and RFU — enhancement. These should be treated in the same way as a ...
Page 16
Bus Operations CE# low and RST# high enable device read operations. The device internally decodes upper address inputs to determine the accessed block. ADV# low opens the internal address latches. OE# low activates the outputs and gates selected data ...
Page 17
... P33-65nm In asynchronous page mode, sixteen data words are “sensed” simultaneously from the flash memory array and loaded into an internal page buffer. The buffer word corresponding to the initial address on the address bus is driven onto DQ[15:0] after the initial access delay. The lowest four address bits determine which word of the 16-word page is output from the data buffer at any given time ...
Page 18
... As with any automated device important to assert RST# when the system is reset. When the system comes out of reset, the system processor attempts to read from the flash memory the system boot device CPU reset occurs with no flash memory reset, improper CPU initialization may occur because the flash memory may be providing status information rather than array data ...
Page 19
... Command Set 6.1 Device Command Codes The flash Command User Interface (CUI) provides control of all read, write, and erase operations. The on-chip WSM manages all block-erase and word-program algorithms. Device commands are written to the CUI to control all flash memory device operations. ...
Page 20
Table 6: Command Codes and Definitions (Sheet Mode Code Device Mode Program or Erase 0xB0 Suspend Suspend 0xD0 Suspend Resume 0x60 Block lock Setup 0x01 Block lock Protection 0xD0 Block Unlock 0x2F Block Lock-Down OTP Register or ...
Page 21
P33-65nm Table 7: Command Bus Cycles Mode Command Read Array Read Device Identifier Read Read CFI Read Status Register Clear Status Register Word Program (3) Buffered Program Program Buffered Enhanced Factory Program (4) (BEFP) Erase Block Erase Program/Erase Suspend Suspend ...
Page 22
... Following a device power-up or reset, the device is set to Read Array mode. However, to perform array reads after any other device operation (e.g. write operation), the Read Array command must be issued in order to read from the flash memory array. Please refer to Section 5.1, “Read - Asynchronous Single Word Mode” on page 18 5.3, “ ...
Page 23
... The 2-Gbit devices do not have a unique Device ID associated with them. Each die within the stack can be identified by the ID codes. 7.3 Read CFI The Read CFI command instructs the device to output Common Flash Interface data when read. See Section A.1, “Common Flash Interface” on page 63 information. ...
Page 24
... The device features a 512-word buffer to enable optimum programming performance. For Buffered Programming, data is first written to an on-chip write buffer. Then the buffer data is programmed into the flash memory array in buffer-size increments. This can improve system programming performance significantly over non-buffered programming. (see When the Buffered Programming Setup command is issued, Status Register information is updated and reflects the availability of the buffer ...
Page 25
... After the last data is written to the buffer, the Buffered Programming Confirm command must be issued to the original block address. The WSM begins to program buffer contents to the flash memory array command other than the Buffered Programming Confirm command is written to the device, a command sequence error occurs and SR[7,5,4] are set ...
Page 26
... BEFP programs one block at a time; all buffer data must fall within a single block. Suspend BEFP cannot be suspended. Programming the flash Programming to the flash memory array can occur only when the buffer is full. memory array Notes: 1. Some degradation in performance may occur is this limit is exceeded, but the internal algorithm continues to work properly ...
Page 27
... During the buffer-loading sequence, data is stored to sequential buffer locations starting at address 0x00. Programming of the buffer contents to the flash memory array starts as soon as the buffer is full. If the number of words is less than 512, the remaining buffer locations must be filled with 0xFFFF ...
Page 28
When a programming operation is executing, issuing the Program Suspend command requests the WSM to suspend the programming algorithm at ...
Page 29
... P33-65nm 9.0 Erase Operation Flash erasing is performed on a block basis. An entire block is erased each time an erase command sequence is issued, and only one block is erased at a time. When a block is erased, all bits within that block read as logical ones. The following sections describe block erase operations in detail. ...
Page 30
Register indicates a ready status (SR.7 = 1). The Status Register should be checked for any errors, and then cleared. If the Blank Check operation fails, which means the block is not completely erased, the Status Register bit SR.5 will ...
Page 31
... The following sections describe each security mode in detail. 10.1 Block Locking Individual instant block locking is used to protect user code and/or data within the flash memory array. All blocks power locked state to protect array data from being altered during power transitions. Any block can be locked or unlocked with no latency. ...
Page 32
Figure 9: Block Locking State Diagram Note: LK: Lock Setup Command, 60h; LK/D0h: Unlock Command; ...
Page 33
P33-65nm 10.2 Selectable OTP Blocks P33-65nm provides the backward compatible One Time Programming permanent block lock security feature. Blocks from the main array can be optionally configured as OTP. Ask your local Numonyx Sales representative for details about these selectable ...
Page 34
Register When non-array reads are performed in asynchronous page mode only the first data is valid and all subsequent data are undefined. When a non-array read operation occurs as synchronous burst mode, the same word of data requested will ...
Page 35
P33-65nm 11.2 Read Configuration Register (RCR)(Easy BGA) The RCR is a 16-bit read/write register used to select the read mode (synchronous or asynchronous), and to configure synchronous burst characteristics of the device. To modify RCR settings, use the Configure Read ...
Page 36
Table 13: Read Configuration Register Description (Sheet Burst Wrap (BW) 3 2:0 Burst Length (BL[2:0]) 11.2.1 Read Mode (RCR.15) The Read Mode (RM) bit selects synchronous burst-mode or asynchronous page-mode operation for the device. When the RM ...
Page 37
P33-65nm Figure 10: First-Access Latency Count CLK [C] Valid A ddress [A] Address ADV# [V] Code 0 (Reserved) Valid DQ [D/Q] Output 15-0 Code 1 (Reserved ) DQ [D/Q] 15-0 Code 2 DQ [D/Q] 15-0 Code 3 DQ [D/Q] 15-0 ...
Page 38
Figure 11: Example Latency Count Setting Using Code 3 CLK CE# ADV# A[MAX:0] A[MAX:1] D[15:0] 11.2.3 End of Word Line (EOWL) Considerations The delay may occur when a burst sequence access crosses a 16-word boundary. That is, A[4:1] of start ...
Page 39
P33-65nm Table 15: End of Wordline Data and WAIT state Comparison Latency Count Data States 1 Not Supported Not Supported ...
Page 40
Table 17: Burst Sequence Word Ordering Start Burst Addr. Wrap 4-Word Burst (DEC) (RCR.3) (BL[2:0] = 0b001 0-1-2 1-2-3 2-3-0 3-0-1 ...
Page 41
... Burst Length (RCR[2:0]) The Burst Length bits (BL[2:0]) select the linear burst length for all synchronous burst reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word or continuous word. Continuous burst accesses are linear only, and do not wrap within any word length boundaries (see Table 17, “ ...
Page 42
Figure 13: OTP Register Map 0x109 0x102 0x91 0x8A 0x89 0x88 0x85 0x84 0x81 0x80 11.3.1 Reading the OTP Registers The OTP Registers can be read from OTP-RA address. To read the OTP Register, first issue the Read Device Identifier ...
Page 43
P33-65nm The device programs the 64-bit and Sixteen 128-bit user-programmable Protection Registers data 16 bits at a time (see on page 81). Issuing the Program OTP Register command outside of the OTP Register’s address space causes a program error (SR.4 ...
Page 44
... Asserting RST# during a system reset is important with automated program/erase devices because systems typically expect to read from flash memory when coming out of reset CPU reset occurs without a flash memory reset, proper CPU initialization may not occur. This is because the flash memory may be providing status information, instead of array data as expected ...
Page 45
... Two-line control and correct de-coupling capacitor selection suppress transient voltage peaks. Because flash memory devices draw their power from VCC, VPP, and VCCQ, each power connection should have a 0.1 µF ceramic capacitor to ground. High-frequency, inherently low-inductance capacitors should be placed as close as possible to package leads ...
Page 46
Maximum Ratings and Operating Conditions 13.1 Absolute Maximum Ratings Warning: Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are stress ratings only. Table 19: Absolute Maximum Ratings Parameter Temperature under bias Storage temperature Voltage ...
Page 47
P33-65nm 14.0 Electrical Specifications 14.1 DC Current Characteristics Table 21: DC Current Characteristics (Sheet Sym Parameter 512-Mbit/ 1-Gbit I Input Load Current LI 2-Gbit Output Leakage 512-Mbit/ Current 1-Gbit I LO DQ[15:0], WAIT 2-Gbit 512-Mbit 1-Gbit I ...
Page 48
Table 21: DC Current Characteristics (Sheet Sym Parameter I VPP Blank Check PPBC Notes: 1. All currents are RMS unless noted. Typical values at typical VCC the average current measured over any 5ms ...
Page 49
P33-65nm 15.0 AC Characteristics 15.1 AC Test Conditions Figure 15: AC Input/Output Reference Waveform V CCQ Input V /2 CCQ 0V Note: AC test inputs are driven at VCCQ for Logic "1" and 0 V for Logic "0." Input/output timing ...
Page 50
Figure 17: Clock Input AC Waveform CLK [C] 15.2 Capacitance Table 24: Capacitance Sym Parameter Address, Data, CE#, C Input Capacitance WE#, OE#, RST#, IN CLK, ADV#, WP# C Output Capacitance Data, WAIT OUT Note: Sampled, not 100% tested. Datasheet ...
Page 51
P33-65nm 15.3 AC Read Specifications Table 25: AC Read Specifications - (Sheet Num Symbol Asynchronous Specifications R1 t Read cycle time AVAV R2 t Address to output valid AVQV R3 t CE# low to output valid ELQV ...
Page 52
Table 25: AC Read Specifications - (Sheet Num Symbol Synchronous Specifications (Easy BGA) R301 t Address setup to CLK AVCH/L R302 t ADV# low setup to CLK VLCH/L R303 t CE# low setup to CLK ELCH/L R304 ...
Page 53
P33-65nm Figure 19: Asynchronous Single-Word Read for Easy BGA (ADV# Latch) Address [A] A[4:1][A] R101 R 105 R106 R 104 ADV#[V] CE# [E] OE# [G] R15 WAIT [T] Data [D/Q] Note: WAIT shown deasserted during asynchronous read mode (RCR.10=0, WAIT ...
Page 54
... This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by CE# deassertion after the first word in the burst. Figure 22: Continuous Burst Read, showing an Output Delay Timing for Easy BGA ...
Page 55
P33-65nm Figure 23: Synchronous Burst-Mode Four-Word Read Timing for Easy BGA R302 R301 R306 CLK [C] R2 R101 Address [A] A R105 R105 R106 R102 ADV# [V] R303 CE# [E] OE# [G] R15 WAIT [T] R7 Data [D/Q] Note: WAIT ...
Page 56
Table 26: AC Write Specifications (Sheet Num Symbol Write to Synchronous Read Specifications W19 t WE# high to Clock valid WHCH/L W20 t WE# high to ADV# high WHVH W28 t WE# high to ADV# low WHVL ...
Page 57
P33-65nm Figure 25: Asynchronous Read-to-Write Timing W5 Address [A] W2 CE# [E] WE# [W] OE# [G] Data [D/Q] W1 RST# [P] Note: WAIT deasserted during asynchronous read and during write. WAIT High-Z during write per OE# deasserted. Figure 26: Write-to-Asynchronous ...
Page 58
Figure 27: Synchronous Read-to-Write Timing R301 R302 R306 CLK [C] R2 R101 Address [A] R105 R105 R106 R102 ADV# [V] R303 R3 CE# [E] OE# [G] WE#[W] WAIT [T] Data [D/Q] Note: WAIT shown deasserted and High-Z per OE# deassertion ...
Page 59
P33-65nm Program and Erase Characteristics 15.5 Table 27: Program and Erase Specifications Num Symbol Parameter Program W200 t Single word PROG/W Time Aligned 32-Wd, BP time (32 Words) Aligned 64-Wd, BP time (64 Word) Program Aligned 128-Wd, BP time W250 ...
Page 60
... E F 1-Gbit PC28F00AP33EF* PC28F00AP33BF* PC28F00AP33TF* JS28F00AP33EF* JS28F00AP33BF* JS28F00AP33TF* P33-65nm * F Device Features* Device lithography F = 65nm Parameter Location E = Symmetrical Blocks T = Top Parameter B = Bottom Parameter Product Family ® Numonyx Axcell™ P33 Flash Memory – – CCQ . 2-Gbit PC28F00BP33EF Apr 2010 Order Number: 208043-05 ...
Page 61
... The system software will then know which command set(s) to use to properly perform flash writes, block erases, reads and otherwise control the flash device. ...
Page 62
... Table 30: Example of Query Structure Output of x16 Devices A.1.2 Query Structure Overview The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or database. locations. Table 31: Query Structure 00001-Fh Reserved 00010h CFI query identification string 0001Bh System interface information ...
Page 63
P33-65nm Table 32: CFI Identification Offset Length 10h 3 Query-unique ASCII string “QRY”. Primary Vendor command set and control interface ID code. 13h 2 16-bit ID code for Vendor-specified algorithms. 15h 2 Extended Query Table primary algorithm address. Alternate vendor ...
Page 64
... Numonyx-Specific Extended Query Table Table 34: Device Geometry Definition Offset Length 27h 1 “n” such that device size = 2 Flash device interface code assignment: "n" such that n+1 specifies the bit field that represents the flash device width capabilities as described in the table 28h ...
Page 65
... Pagemode read supported (Note: Only Available for Easy BGA) bit 8 Synchronous read supported (Note: Only Available for Easy BGA) bit 9 Simultaneous operations supported bit 10 Extended Flash Array Blocks supported bit 11 Permanent Block Locking Full Main Array supported bit 12 Permanent Block Locking Partial Main Array supported bit 30 CFI Link(s) to follow bit 31 Another " ...
Page 66
... Table 36: OTP Register Information Offset (1) Length P = 10Ah (Optional flash features and commands) (P+E)h 1 Number of Protection register fields in JEDEC ID space. “00h,” indicates that 256 protection fields are available (P+F)h 4 Protection Field 1: Protection Description (P+10)h This field describes user-available One Time Programmable (P+11)h (OTP) Protection register bytes ...
Page 67
... Datasheet 69 Description n HEX value represents the number of Description (Optional flash features and commands) Hex Add. Code Value 127: --05 32 byte 128: --04 4 129: ...
Page 68
... Symmetrically blocked partitions have one blocking region. Partition size = (Type 1 blocks)x(Type 1 block sizes) + (Type 2 blocks)x(Type 2 block sizes) +…+ (Type n blocks)x(Type n block sizes) Datasheet 70 Description (Optional flash features and commands) P33-65nm See table below Address Len Bot Top 2 ...
Page 69
... Reserved (P+38)h (P+38)h bits 32- Control Mode invalid size in bytes (P+39)h (P+39)h bits 40-46 = Reserved; bit 47 = Legacy flash operation (ignore 23:16 & 39:32) (P+3A)h (P+3A)h Partition Region 1 Erase Block Type 2 Information (P+3B)h (P+3B)h bits 0– y identical-size erase blks in a partition (P+3C)h (P+3C)h bits 16– ...
Page 70
Table 41: Partition and Erase Block Region Information Add. Top 12D: --01 12E: --24 12F: --00 130: --01 131: --00 132: --11 133: --00 134: --00 135: --02 136: --FE 137: --01 138: --00 139: --02 13A: --64 13B: --00 ...
Page 71
... Bit 5 = Link Field & Table relative location Bits 6:7 = Reserved Datasheet 73 1-Gbit Symm Bottom Top Bottom . --00 --FF --00 --00 --00 --FF --00 --00 --80 --FF --80 --80 Description (Optional Flash features and commands 2-Gbit Symm. Symm. Symm. Upper Die Lower Die --FF --FF --FF --FF --FF --FF --FF --FF --FF Add. Value 144: 145: See Table 41, 146: “ ...
Page 72
A.2 Flowcharts Figure 30: Word Program Flowchart Start Command Cycle - Issue Program Command - Address = location to program - Data = 0x40 Data Cycle - Address = location to program - Data = Data to program Check Ready ...
Page 73
... Count ranges for this device are N=0000h to 01FFh. 2. The device outputs the Status Register when read. 3. Write Buffer contents will be programmed at the device start address or destination flash address . Align the start address on a Write Buffer boundary for maximum programming performance (i.e., A address =0) ...
Page 74
... Count ranges for this device are N =0000h to 01FFh. 2. The device outputs the Status Register when read. 3. Write Buffer contents will be programmed at the device start address or destination flash address . Align the start address on a Write Buffer boundary for maximum programming performance (i.e., A address =0) ...
Page 75
P33-65nm Figure 33: BEFP Flowchart Setup Phase Start Issue BEFP Setup Cmd (Data = 0x80) Issue BEFP Confirm Cmd (Data = 00D0h) BEFP Setup Delay Read Status Register Yes (SR.7=0) BEFP Setup Done ? No (SR.7=1) SR Error Handler (User-Defined) ...
Page 76
Figure 34: Block Erase Flowchart Start Command Cycle - Issue Erase command - Address = Block to be erased - Data = 0x20 Confirm Cycle - Issue Confirm command - Address = Block to be erased - Data = Erase ...
Page 77
P33-65nm Figure 35: Block Lock Operations Flowchart Start Lock Setup Write 60h Block Address Lock Confirm Write 01 ,D0,2Fh Block Address Read ID Plane Write 90h Read Block Lock Status Locking No Change ? Yes Read Array Write FFh Any ...
Page 78
Figure 36: Erase Suspend/Resume Flowchart Start Write 0 x70 , (Read Status ) Same Partition Write 0xB0, (Erase Suspend ) Any Address Read Status Register Read Read or Program Program ...
Page 79
P33-65nm Figure 37: OTP Register Programming Flowchart - Read Status Register Command not required - Perform read operation - Read Ready Status on signal SR.7 - Toggle CE# or OE# to update Status Register - See Status Register Flowchart Datasheet ...
Page 80
Figure 38: Status Register Flowchart - Issue Status Register Command - Address = any device address - Data = 0x70 - Read Status Register SR[7:0] - Set/Reset by WSM - Set by WSM - Reset by user - See Clear ...
Page 81
P33-65nm A.3 Write State Machine Show here are the command state transitions (Next State Table) based on incoming commands. Only one partition can be actively programming or erasing at a time. Each partition stays in its last read state (Read ...
Page 82
Table 43: Next State Table for P3x-65nm (Sheet Current Chip State (FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) (B0) (70h) (50h) Setup (8) BP Load 1 (8) BP Load 2 Buffer BP Confirm Ready (Error [Botch]) Pgm ...
Page 83
P33-65nm Table 43: Next State Table for P3x-65nm (Sheet Current Chip State (FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) (B0) (70h) (50h) EFI Setup Sub-function Setup Sub-op-code Sub-function Load 2 in Erase Suspend if word count >0, ...
Page 84
Table 44: Output Next State Table for P3x-65nm Current Chip State (FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) (B0) (70h) (50h) BEFP Setup, BEFP Pgm & Verify Busy, Erase Setup, OTP Setup, BP Setup, Load 1, Load 2 BP Setup, ...
Page 85
... Two bytes, or sixteen bits 1024 bits 1024 bytes 1024 words 1,048,576 bits 1,048,576 bytes 1,048,576 words 1,000 1,000,000 A group of bits, bytes, or words within the flash memory array that erase simultaneously. An array block that is usually used to store code and/or data. Apr 2010 Order Number:208043-05 ...
Page 86
Appendix C Revision History Date Revision Description Jan 2008 01 Initial release Add Top/Bottom device information such as memory map, device ID, CFI, ordering information etc. Add 40Mhz specification for TSOP package. Add a Note to clarify the SR output ...