JS28F512P33BFD Micron Technology Inc, JS28F512P33BFD Datasheet - Page 43

• Manufacturer Part Number: JS28F512P33BFD
• Manufacturer: Micron Technology Inc

Specifications of JS28F512P33BFD

• Cell Type: NOR
• Density: 512Mb
• Access Time (max): 105/17ns
• Interface Type: Parallel/Serial
• Boot Type: Bottom
• Address Bus: 25b
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 8.5 to 9.5V
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 32M
• Supply Current: 31mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Supplier Unconfirmed

P33-65nm
Note:
11.3.3
Caution:
Datasheet
45
The device programs the 64-bit and Sixteen 128-bit user-programmable Protection
Registers data 16 bits at a time (see
on page
address space causes a program error (SR.4 set). Attempting to program a locked OTP
Register causes a program error (SR.4 set) and a lock error (SR.1 set).
When programming the OTP bits in the OTP Registers for a Top Parameter Device, the
upper addresses A[Max:17] must also be driven high (V
packages.
Locking the OTP Registers
Each OTP Register can be locked by programming its respective lock bit in the Lock
Register. To lock a OTP Register, program the corresponding bit in the Lock Register by
issuing the Program Lock Register command, followed by the desired Lock Register
data (see
addresses of the Lock Registers are 0x80 for register 0 and 0x89 for register 1. These
addresses are used when programming the Lock Registers (see
Identifier Information” on page
Bit 0 of Lock Register 0 is already programmed during the manufacturing process at
Numonyx factory, locking the lower half segment of the first 128-bit OTP Register. Bit 1
of Lock Register 0 can be programmed by the user to lock the upper half of the first
128-bit OTP Register. When programming Bit 1 of Lock Register 0, all other bits need to
be left as ‘1’ such that the data programmed is 0xFFFD.
Lock Register 1 controls the locking of the upper sixteen 128-bit OTP Registers. Each
bit of Lock Register 1 corresponds to a specific 128-bit OTP Registers; e.g.,
programming a bit in LR1.0 locks the corresponding OTP Register 1.
After being locked, the OTP Registers cannot be unlocked.
81). Issuing the Program OTP Register command outside of the OTP Register’s
Section 6.2, “Device Command Bus Cycles” on page
24).
Figure 37, “OTP Register Programming Flowchart”
IH
) for TSOP and Easy BGA
22). The physical
Table 8, “Device
Order Number:208043-05
Apr 2010