ISP1507B1HNTM STEricsson, ISP1507B1HNTM Datasheet - Page 56

• Manufacturer Part Number: ISP1507B1HNTM
• Manufacturer: STEricsson

Specifications of ISP1507B1HNTM

• Lead Free Status / RoHS Status: Compliant

Table 42.
Table 43.
CD00269905
Product data sheet
Bit
Symbol
Reset
Access
Bit
7 to 4
3
2
1 to 0
Symbol
-
BVALID_FALL
BVALID_RISE
-
PWR_CTRL - Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit allocation
PWR_CTRL - Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit description
11.1.14 PWR_CTRL register
R/W/S/C
11.2 Extended register set
7
0
This register controls various aspects of the ISP1507x1. See
Addresses 00h to 3Fh of the extended register set directly map to the immediate set. This
means a read, write, set, or clear operation to these extended addresses will operate on
the immediate register set.
Addresses 40h to FFh are not implemented. Operating on these addresses may result in
undefined behavior of the PHY.
Description
reserved; the link must never write logic 1 to these bits.
BVALID fall: Enables RXCMDs for HIGH-to-LOW transitions on BVALID. When BVALID
changes from HIGH to LOW, the ISP1507x1 will send an RXCMD to the link with the ALT_INT
bit set to logic 1.
This bit is optional and is not necessary for OTG devices. This bit is provided for debugging
purposes. The session valid comparator should be used instead.
BVALID rise: Enables RXCMDs for LOW-to-HIGH transitions on BVALID. When BVALID
changes from LOW to HIGH, the ISP1507x1 will send an RXCMD to the link with the ALT_INT
bit set to logic 1.
This bit is optional and is not necessary for OTG devices. This bit is provided for debugging
purposes. The session valid comparator should be used instead.
reserved; the link must never write logic 1 to these bits.
R/W/S/C
6
0
reserved
R/W/S/C
5
0
Rev. 03 — 26 July 2010
R/W/S/C
4
0
ISP1507A1; ISP1507B1
BVALID_
R/W/S/C
FALL
3
0
BVALID_
R/W/S/C
RISE
ULPI HS USB OTG transceiver
2
0
Table
R/W/S/C
42.
© ST-ERICSSON 2010. All rights reserved.
1
0
reserved
R/W/S/C
0
0
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