ISP1507B1HNTM STEricsson, ISP1507B1HNTM Datasheet - Page 55

• Manufacturer Part Number: ISP1507B1HNTM
• Manufacturer: STEricsson

Specifications of ISP1507B1HNTM

• Lead Free Status / RoHS Status: Compliant

Table 38.
Table 39.
Table 40.
Table 41.
Legend: * reset value
CD00269905
Product data sheet
Bit
2
1
0
Bit
Symbol
Reset
Access
Bit
7 to 2
1
0
Bit
7 to 0
Symbol
SCRATCH
[7:0]
Symbol
SESS_VALID_L
VBUS_VALID_L
HOST_DISCON_L
Symbol
-
LINESTATE1
LINESTATE0
USB_INTR_L - USB Interrupt Latch register (address R = 14h) bit description
DEBUG - Debug register (address R = 15h) bit allocation
DEBUG - Debug register (address R = 15h) bit description
SCRATCH - Scratch register (address R = 16h to 18h, W = 16h, S = 17h, C = 18h) bit description
11.1.10 SCRATCH register
11.1.12 Access extended register set
11.1.13 Vendor-specific registers
11.1.11 Reserved
11.1.9 DEBUG register
R
7
0
Access
R/W/S/C 00h*
The bit allocation of the DEBUG register is given in
current value of signals useful for debugging.
This is an empty register for testing purposes; see
Registers 19h to 2Eh are not implemented. Operating on these addresses will have no
effect on the ISP1507x1.
Address 2Fh does not contain register data. Instead it links to the extended register set.
The immediate register set maps to the lower end of the extended register set.
Addresses 30h to 3Fh contain vendor-specific registers.
Description
reserved
Line state 1: Contains the current value of LINESTATE 1.
Line state 0: Contains the current value of LINESTATE 0.
Description
Session valid latch: Automatically set when an unmasked event occurs on SESS_VLD.
Cleared when this register is read.
V
Cleared when this register is read.
Host disconnect latch: Automatically set when an unmasked event occurs on
HOST_DISCON. Cleared when this register is read.
BUS
Value Description
R
6
0
valid latch: Automatically set when an unmasked event occurs on A_VBUS_VLD.
Scratch: This is an empty register byte for testing purposes. Software can read,
write, set, and clear this register. The functionality of the ISP1507x1 will not be
affected.
R
5
0
reserved
Rev. 03 — 26 July 2010
R
4
0
ISP1507A1; ISP1507B1
R
3
0
Table
Table
41.
ULPI HS USB OTG transceiver
R
39. This register indicates the
2
0
…continued
STATE1
© ST-ERICSSON 2010. All rights reserved.
LINE
R
1
0
STATE0
LINE
R
0
0
55 of 78