ISP1507B1HNTM STEricsson, ISP1507B1HNTM Datasheet - Page 20

• Manufacturer Part Number: ISP1507B1HNTM
• Manufacturer: STEricsson

Specifications of ISP1507B1HNTM

• Lead Free Status / RoHS Status: Compliant

10. Protocol description
CD00269905
Product data sheet
10.1 ULPI references
10.2 Power-On Reset (POR)
10.3 Power-up, reset, and bus idle sequence
The following subsections describe the protocol for using the ISP1507x1.
The ISP1507x1 provides a 12-pin ULPI interface to communicate with the link. It is highly
recommended that you read UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 and
UTMI+ Specification Rev. 1.0.
An internal POR is generated when REG1V8 rises above V
t
below V
voltage on REG1V8 is generated from V
To give a better view of the functionality,
internal POR starts with logic 0 at t0. At t1, the detector will see the passing of the trip
level so that POR turns to logic 1 and a delay element will add another t
drops to logic 0. If REG1V8 dips from t2 to t3 for > t
generated. If the dip at t4 to t5 is too short, that is, < t
will not react and will remain LOW.
Figure 4
On power-up, the ISP1507x1 performs an internal power-on reset and asserts DIR to
indicate to the link that the ULPI bus cannot be used. When the internal PLL is stable, the
ISP1507x1 deasserts DIR. The power-up time depends on the V
crystal start-up time, and PLL start-up time t
ISP1507x1 drives the NXT pin to LOW and drives DATA[7:0] with RXCMD values. When
DIR is deasserted, the link must drive the data bus to a valid level. By default, the link
must drive data to LOW. When the ISP1507x1 initially deasserts DIR on power-up, the link
must ignore all RXCMDs until it resets the ISP1507x1. Before beginning USB packets, the
link must set the RESET bit in the FUNC_CTRL register (see
ISP1507x1. After the RESET bit is set, the ISP1507x1 will assert DIR until the internal
reset completes. The ISP1507x1 will automatically deassert DIR and clear the RESET bit
when reset has completed. After every reset, an RXCMD is sent to the link to update USB
status information. After this sequence, the ULPI bus is ready for use and the link can start
USB operations.
w(REG1V8_H)
Fig 3.
POR(trip)
shows a typical start-up sequence.
Internal power-on reset timing
t0
. The internal POR pulse will also be generated whenever REG1V8 drops
for more than t
t1
t
PORP
Rev. 03 — 26 July 2010
w(REG1V8_L)
t2
Figure 3
CC
ISP1507A1; ISP1507B1
, and then rises above V
.
startup(o)(CLOCK)
t3
t
PORP
shows a possible curve of REG1V8. The
w(REG1V8_L)
w(REG1V8_L)
t4
ULPI HS USB OTG transceiver
. Whenever DIR is asserted, the
POR(trip)
t5
Section
, another POR pulse is
, the internal POR pulse
CC
POR(trip)
, for at least
supply rise time, the
© ST-ERICSSON 2010. All rights reserved.
11.1.2) to reset the
004aaa751
PORP
REG1V8
V
POR
POR(trip)
again. The
before it
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