ISP1507B1HNTM STEricsson, ISP1507B1HNTM Datasheet - Page 54

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ISP1507B1HNTM

Manufacturer Part Number
ISP1507B1HNTM
Description
Manufacturer
STEricsson
Datasheet

Specifications of ISP1507B1HNTM

Lead Free Status / RoHS Status
Compliant

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0
Table 35.
Table 36.
Table 37.
Table 38.
CD00269905
Product data sheet
Bit
Symbol
Reset
Access
Bit
7 to 5
4
3
2
1
0
Bit
Symbol
Reset
Access
Bit
7 to 5
4
3
Symbol
-
ID_GND_L
SESS_END_L
Symbol
-
ID_GND
SESS_END
SESS_VALID
VBUS_VALID
HOST_DISCON
USB_INTR_STAT - USB Interrupt Status register (address R = 13h) bit allocation
USB_INTR_STAT - USB Interrupt Status register (address R = 13h) bit description
USB_INTR_L - USB Interrupt Latch register (address R = 14h) bit allocation
USB_INTR_L - USB Interrupt Latch register (address R = 14h) bit description
11.1.7 USB_INTR_STAT register
11.1.8 USB_INTR_L register
R
R
X
7
7
0
This register (see
The bits of the USB_INTR_L register are automatically set by the ISP1507x1 when an
unmasked change occurs on the corresponding interrupt source signal. The ISP1507x1
will automatically clear all bits when the link reads this register, or when the PHY enters
low-power or serial mode.
Remark: It is optional for the link to read this register when the clock is running because
all signal information will automatically be sent to the link through the RXCMD byte.
The bit allocation of this register is given in
reserved
reserved
Description
reserved
ID ground latch: Automatically set when an unmasked event occurs on ID_GND. Cleared
when this register is read.
Session end latch: Automatically set when an unmasked event occurs on SESS_END.
Cleared when this register is read.
X
R
Description
reserved
ID ground: Reflects the current value of the ID detector circuit.
Session end: Reflects the current value of the session end voltage comparator.
Session valid: Reflects the current value of the session valid voltage comparator.
V
Host disconnect: Reflects the current value of the host disconnect detector.
R
6
6
0
BUS
valid: Reflects the current value of the V
Table
R
R
5
X
5
0
Rev. 03 — 26 July 2010
35) indicates the current value of the interrupt source signal.
ID_GND_L
ID_GND
R
R
4
0
4
0
SESS_END
ISP1507A1; ISP1507B1
SESS_
END_L
Table
R
R
3
0
3
0
BUS
37.
valid voltage comparator.
VALID_L
SESS_
SESS_
VALID
ULPI HS USB OTG transceiver
R
R
2
0
2
0
VALID_L
VBUS_
VBUS_
VALID
© ST-ERICSSON 2010. All rights reserved.
R
R
1
0
1
0
DISCON_L
DISCON
HOST_
HOST_
R
R
0
0
0
0
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