ISP1507B1HNTM STEricsson, ISP1507B1HNTM Datasheet - Page 31

• Manufacturer Part Number: ISP1507B1HNTM
• Manufacturer: STEricsson

Specifications of ISP1507B1HNTM

• Lead Free Status / RoHS Status: Compliant

CD00269905
Product data sheet
Fig 10. Example of register write, register read, extended register write, and extended register read
DATA[7:0]
CLOCK
NXT
STP
DIR
AD indicates the address byte. D indicates the data byte.
10.6 Register read and write operations
10.7 USB reset and high-speed detection handshake (chirp)
(REGW)
TXCMD
register write
immediate
Figure 10
addressing and extended addressing register operations. Extended register addressing is
optional for links. Note that register operations will be aborted if the ISP1507x1
unexpectedly asserts DIR during the operation. When a register operation is aborted, the
link must retry until successful. For more information on register operations, refer to
UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1.
Figure 11
handshake (chirp). The sequence is shown for hosts and peripherals.
show all RXCMD updates and timing is not to scale. The sequence is as follows:
1. USB reset: The host detects a peripheral attachment as low-speed if DM is HIGH and
2. High-speed detection handshake (chirp)
D
as full-speed if DP is HIGH. If a host detects a low-speed peripheral, it does not follow
the remainder of this protocol. If a host detects a full-speed peripheral, it resets the
peripheral by writing to the Function Control register (see
XCVRSELECT[1:0] = 00b (high-speed) and TERMSELECT = 0b are then set which
drives SE0 on the bus (DP and DM are connected to ground through 45 Ω). The host
also sets OPMODE[1:0] = 10b for correct chirp transmit and receive. The start of SE0
is labeled T
Remark: To receive chirp signaling, the host must also consider the high-speed
differential receiver output. The host controller must interpret LINESTATE[1:0] as
shown in
a. Peripheral chirp: After detecting SE0 for no less than 2.5 μs, if the peripheral is
capable of high-speed, it sets XCVRSELECT[1:0] = 00b (high-speed) and
OPMODE[1:0] = 10b (chirp). The peripheral immediately follows this with a
TXCMD (NOPID), transmitting a Chirp K for no less than 1 ms and ending no more
shows the sequence of events for USB reset and high-speed detection
shows register read and write sequences. The ISP1507x1 supports immediate
TXCMD
(EXTW) AD D
register write
Table
extended
0
.
13.
Rev. 03 — 26 July 2010
TXCMD
(REGR)
register read
immediate
D
ISP1507A1; ISP1507B1
TXCMD
(EXTW)
register read
extended
AD
ULPI HS USB OTG transceiver
D
Section
© ST-ERICSSON 2010. All rights reserved.
11.1.2).
Figure 11
004aaa710
does not
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