ISP1507B1HNTM STEricsson, ISP1507B1HNTM Datasheet - Page 13

• Manufacturer Part Number: ISP1507B1HNTM
• Manufacturer: STEricsson

Specifications of ISP1507B1HNTM

• Lead Free Status / RoHS Status: Compliant

CD00269905
Product data sheet
8.9.12 RESET_N
8.9.13 DIR
8.9.14 STP
8.9.11 XTAL1 and XTAL2
XTAL1 is the crystal input, and XTAL2 is the crystal output. The allowed frequency on the
XTAL1 pin depends on the ISP1507x1 product version.
If the link requires a 60 MHz clock from the ISP1507x1, then either a crystal must be
attached, or a clock of the same frequency must be driven into XTAL1, with XTAL2 left
floating.
If a crystal is attached, it requires external load capacitors to GND on each terminal of the
crystal. For details, see
If at any time the system wants to stop the clock on XTAL1, the link must first put the
ISP1507x1 into low-power mode. The clock on XTAL1 must be restarted before
low-power mode is exited.
An active-LOW asynchronous reset pin that resets all circuits in the ISP1507x1. The
ISP1507x1 contains an internal power-on reset circuit, and therefore using the RESET_N
pin is optional. If RESET_N is not used, it must be connected to V
For details on using RESET_N, see
ULPI direction output pin. Controls the direction of the data bus. By default, the
ISP1507x1 holds DIR at LOW, causing the data bus to be an input. When DIR is LOW, the
ISP1507x1 listens for data from the link. The ISP1507x1 pulls DIR to HIGH only when it
has data to send to the link, which is for one of two reasons:
The DIR pin can also be 3-stated by driving CHIP_SELECT_N to HIGH.
For details on DIR usage, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1.
ULPI stop input pin. The link must assert STP to signal the end of a USB transmit packet
or a register write operation. When DIR is asserted, the link can optionally assert STP to
abort the ISP1507x1, causing it to deassert DIR in the next clock cycle. A weak pull-up
resistor is incorporated into the STP pin as part of the interface protect feature. For details,
see
The STP input will be ignored when CHIP_SELECT_N is driven to HIGH.
For details on STP usage, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1.
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To send USB receive data, RXCMD status updates, and register read data to the link.
To block the link from driving the data bus during power-up, reset, and low-power
(suspend) mode.
Section
10.3.1.
Rev. 03 — 26 July 2010
Section
17.
Section
ISP1507A1; ISP1507B1
10.3.2.
ULPI HS USB OTG transceiver
CC(I/O)
© ST-ERICSSON 2010. All rights reserved.
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