ISP1507B1HNTM STEricsson, ISP1507B1HNTM Datasheet - Page 53

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ISP1507B1HNTM

Manufacturer Part Number
ISP1507B1HNTM
Description
Manufacturer
STEricsson
Datasheet

Specifications of ISP1507B1HNTM

Lead Free Status / RoHS Status
Compliant

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0
Table 31.
Table 32.
Table 33.
Table 34.
CD00269905
Product data sheet
Bit
Symbol
Reset
Access
Bit
7 to 5
4
3
2
1
0
Bit
Symbol
Reset
Access
Bit
7 to 5
4
3
2
1
0
Symbol
-
ID_GND_R
SESS_END_R
SESS_VALID_R
VBUS_VALID_R
HOST_DISCON_
R
Symbol
-
ID_GND_F
SESS_END_F
SESS_VALID_F Session valid fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on
VBUS_VALID_F V
HOST_DISCON
_F
USB_INTR_EN_R_E - USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh, W = 0Dh,
S = 0Eh, C = 0Fh) bit allocation
USB_INTR_EN_R_E - USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh, W = 0Dh,
S = 0Eh, C = 0Fh) bit description
USB_INTR_EN_F_E - USB Interrupt Enable Falling Edge register (address R = 10h to 12h, W = 10h,
S = 11h, C = 12h) bit allocation
USB_INTR_EN_F_E - USB Interrupt Enable Falling Edge register (address R = 10h to 12h, W = 10h,
S = 11h, C = 12h) bit description
11.1.6 USB_INTR_EN_F_E register
R/W/S/C
R/W/S/C
7
0
7
0
The bits in this register enable interrupts and RXCMDs to be sent when the corresponding
bits in the USB_INTR_STAT register change from logic 1 to logic 0. By default, all
transitions are enabled. See
Description
reserved
ID ground fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on ID_GND.
Session end fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on
SESS_END.
SESS_VLD.
A_VBUS_VLD.
Host disconnect fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on
HOST_DISCON.
reserved
R/W/S/C
Description
reserved
ID ground rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on ID_GND.
Session end rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on
SESS_END.
Session valid rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on
SESS_VLD.
V
A_VBUS_VLD.
Host disconnect rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on
HOST_DISCON.
reserved
R/W/S/C
BUS
BUS
6
0
6
0
valid fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on
valid rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on
R/W/S/C
R/W/S/C
5
0
5
0
Rev. 03 — 26 July 2010
ID_GND_R
ID_GND_F
Table
R/W/S/C
R/W/S/C
4
1
4
1
33.
ISP1507A1; ISP1507B1
R/W/S/C
R/W/S/C
END_R
END_F
SESS_
SESS_
3
1
3
1
VALID_R
VALID_F
R/W/S/C
R/W/S/C
SESS_
SESS_
ULPI HS USB OTG transceiver
2
1
2
1
VALID_R
R/W/S/C
VALID_F
R/W/S/C
VBUS_
VBUS_
© ST-ERICSSON 2010. All rights reserved.
1
1
1
1
DISCON_R
DISCON_F
R/W/S/C
R/W/S/C
HOST_
HOST_
0
1
0
1
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