UJA1061TW,512 NXP Semiconductors, UJA1061TW,512 Datasheet - Page 65

• Manufacturer Part Number: UJA1061TW,512
• Manufacturer: NXP Semiconductors

Specifications of UJA1061TW,512

• Number Of Transceivers: 1
• Power Down Mode: Sleep/Standby
• Operating Supply Voltage (min): 5.5V
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 27.
T
voltages are defined with respect to ground. Positive currents flow into the IC.
[1]
[2]
[3]
[4]
[5]
UJA1061_6
Product data sheet
Symbol
t
Interrupt output; pin INTN
t
Oscillator
f
RSTNL
INTN
osc
vj
=
All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at T
wafer level (pretesting). Cased products are 100 % tested at T
test conditions to cover the specified temperature and power supply voltage range.
SPI timing is guaranteed for V
so at these lower voltages a lower maximum SPI communication speed must be observed.
t
1 kΩ/1 kΩ/10 nF; 1 kΩ/1 kΩ/6.8 nF; 1 kΩ/open/1 nF; see
bit
−
δ1 δ3
δ2 δ4
40
= selected bit time, depends on LSC-bit; 50 μs or 96 μs (20 kbit/s or 10.4 kbit/s respectively); bus load conditions (R
,
,
°
C to + 150
Dynamic characteristics
=
=
t
------------------------------ -
t
------------------------------- -
bus rec
bus rec
Parameter
reset lengthening
time
interrupt release
oscillator input
frequency
2 t
2
(
(
×
×
°
t
) min
) max
bit
C; V
bit
(
(
)
Fig 23. Timing test circuit for CAN transceiver
BAT42
)
BAT42
= 5.5 V to 52 V; V
voltages down to 5 V. For V
[1]
Conditions
after internal or external reset
has been released; RLC = 0
after internal or external reset
has been released; RLC =1
after SPI has read out the
Interrupt register
…continued
All information provided in this document is subject to legal disclaimers.
RXDC
TXDC
10 pF
13
14
BAT14
Rev. 06 — 9 March 2010
32
UJA1061
BAT42
Figure 25
23
= 5.5 V to 27 V; V
GND
amb
27
BAT42
BAT14
24
22
21
19
= 25 °C (final testing). Both pretesting and final testing use correlated
and
Fault-tolerant CAN/LIN fail-safe system basis chip
RTH
CANL
CANH
RTL
voltages down to 4.5 V the guaranteed SPI timing values double,
Figure
500 Ω
R RTL
BAT42
R RTH
500 Ω
26.
Min
0.9
18
2
460.8
≥
GENERATION
V
BAT14
FAILURE
BAT
GND
V
−
CC
1 V; unless otherwise specified. All
V
CC
Typ
-
-
-
512
C CAN_L
C CAN_H
UJA1061
Max
1.1
22
-
563.2
© NXP B.V. 2010. All rights reserved.
001aad804
R CAN_L
R CAN_H
amb
1
/R
= 125 °C on
2
/C
1
Unit
ms
ms
μs
kHz
):
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