UJA1061TW,512 NXP Semiconductors, UJA1061TW,512 Datasheet - Page 13

• Manufacturer Part Number: UJA1061TW,512
• Manufacturer: NXP Semiconductors

Specifications of UJA1061TW,512

• Number Of Transceivers: 1
• Power Down Mode: Sleep/Standby
• Operating Supply Voltage (min): 5.5V
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
UJA1061_6
Product data sheet
6.4.1 Watchdog start-up behavior
6.4.2 Watchdog window behavior
The following corrupted watchdog accesses result in an immediate system reset:
Any microcontroller driven mode change is synchronized with a watchdog access by
reading the mode information and the watchdog period information from the same
register. This enables an easy software flow control with defined watchdog behavior when
switching between different software modules.
Following any reset event the watchdog is used to monitor the ECU start-up procedure. It
observes the behavior of the RSTN pin for any clamping condition or interrupted reset
wire. In case the watchdog is not properly served within t
and the monitoring procedure is restarted. In case the watchdog is again not properly
served, the system enters Fail-safe mode (see also
modes).
Whenever the SBC enters Normal mode, the Window mode of the watchdog is activated.
This ensures that the microcontroller operates within the required speed; a too fast as well
as a too slow operation will be detected. Watchdog triggering using the Window mode is
illustrated in
Fig 4.
•
•
Illegal watchdog period coding; only ten different codes are valid
Illegal operating mode coding; only six different codes are valid
trigger
via SPI
Watchdog triggering using Window mode
Figure
All information provided in this document is subject to legal disclaimers.
trigger point
last
4.
trigger
restarts
period
Rev. 06 — 9 March 2010
too early
(with different duration if
trigger restarts period
earliest possible
Fault-tolerant CAN/LIN fail-safe system basis chip
trigger point
period
50 %
desired)
trigger
via SPI
trigger window
Figure
too early
latest possible
trigger point
WD(init)
100 %
new period
possible
earliest
trigger
3, Start-up and Restart
50 %
point
, another reset is forced
window
trigger
possible
trigger
latest
100 %
point
UJA1061
© NXP B.V. 2010. All rights reserved.
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