UJA1061TW,512 NXP Semiconductors, UJA1061TW,512 Datasheet - Page 35

• Manufacturer Part Number: UJA1061TW,512
• Manufacturer: NXP Semiconductors

Specifications of UJA1061TW,512

• Number Of Transceivers: 1
• Power Down Mode: Sleep/Standby
• Operating Supply Voltage (min): 5.5V
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 9.
[1]
[2]
UJA1061_6
Product data sheet
Bit
5
4
3
2
1
0
This bit is cleared automatically upon each overflow event. It has to be set in software each time the interrupt behavior is required
(fail-safe behavior).
WEN (in the System Configuration register) has to be set to activate the WAKE port function globally.
Interrupt Enable register and Interrupt Enable Feedback register bit description
Symbol
CANFIE
LINFIE
WIE
WDRIE
CANIE
LINIE
6.13.7 Interrupt register
The Interrupt register allows the cause of an interrupt event to be read. The register is
cleared upon a read access and upon any reset event. Hardware ensures that no interrupt
event is lost in case there is a new interrupt forced while reading the register. After reading
the Interrupt register pin INTN is released for t
INTN.
The interrupts can be classified into two groups:
•
•
Description
CAN Failure Interrupt
Enable
LIN Failure Interrupt
Enable
WAKE Interrupt
Enable
Watchdog Restart
Interrupt Enable
CAN Interrupt Enable
LIN Interrupt Enable
Timing critical interrupts which require immediate reaction (SPI clock count failure
which needs a new SPI command to be resent immediately, and a BAT failure which
needs critical data to be saved immediately into the nonvolatile memory)
Interrupts which do not require an immediate reaction (overtemperature, Ground Shift,
CAN and LIN failures, V1, V2 and V3 failures and the wake-ups via CAN, LIN and
WAKE. These interrupts will be signalled in Normal mode to the microcontroller once
per watchdog period (maximum); this prevents overloading the microcontroller with
unexpected interrupt events (e.g. a chattering CAN failure). However, these interrupts
are reflected in the Interrupt register
[2]
All information provided in this document is subject to legal disclaimers.
Rev. 06 — 9 March 2010
Value
1
0
1
0
1
0
1
0
0
1
0
1
Function
any change of the CAN Failure status bits forces an
interrupt
no interrupt forced
any change of the LIN Failure status bits forces an interrupt
no interrupt forced
a negative edge at pin WAKE generates an interrupt in
Normal mode, Flash mode or Standby mode
a negative edge at pin WAKE generates a reset in Standby
mode; No interrupt in any other mode
a watchdog restart during watchdog OFF generates an
interrupt
no interrupt forced
CAN-bus event results in a wake-up interrupt in Standby
mode and in Normal or Flash mode (unless CAN is in
Active mode already)
CAN-bus event results in a reset in Standby mode; No
interrupt in any other mode
LIN-bus event results in a wake-up interrupt in Standby
mode and in Normal or Flash mode (unless LIN is in Active
mode already)
LIN-bus event results in a reset in Standby mode; no
interrupt in any other mode
Fault-tolerant CAN/LIN fail-safe system basis chip
INTN
to guarantee an edge event at pin
…continued
UJA1061
© NXP B.V. 2010. All rights reserved.
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