UJA1061TW,512 NXP Semiconductors, UJA1061TW,512 Datasheet - Page 51

• Manufacturer Part Number: UJA1061TW,512
• Manufacturer: NXP Semiconductors

Specifications of UJA1061TW,512

• Number Of Transceivers: 1
• Power Down Mode: Sleep/Standby
• Operating Supply Voltage (min): 5.5V
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 26.
T
voltages are defined with respect to ground. Positive currents flow into the IC.
UJA1061_6
Product data sheet
Symbol
V
Enable output; pin EN
I
I
V
Interrupt output; pin INTN
I
CAN transmit data input; pin TXDC
V
V
R
CAN receive data output; pin RXDC
I
I
Fault-tolerant CAN-bus lines; pins CANH and CANL
V
V
V
V
V
V
OH
OL
OL
OH
OL
vj
IL(th)
OL
IH
IL
dif(CANH-CANL)
se(CANH)
se(CANL)
det(HxBAT)
det(LxBAT)
det(GSD)(CANH)
TXDC(pu)
=
−
40
°
C to +150
,
Static characteristics
°
C; V
Parameter
LOW-level input
threshold voltage
HIGH-level output
current
LOW-level output
current
LOW-level output
voltage
LOW-level output
current
HIGH-level input
voltage
LOW-level input
voltage
TXDC pull-up resistor V
HIGH-level output
current
LOW-level output
current
differential receiver
threshold voltage
pin CANH single
ended receiver
threshold voltage
pin CANL single
ended receiver
threshold voltage
detection threshold
voltage for bus
failures HxBAT and
LxBAT
pin CANH ground
shift detection
threshold voltage
BAT42
= 5.5 V to 52 V;V
[1]
…continued
All information provided in this document is subject to legal disclaimers.
Conditions
V
V
I
V
V
V
Active mode, On-line, Partial
Networking or On-Line Listen
mode; V
and bus failures H//, L//,
HxGND and LxVCC
Active mode, On-line, Partial
Networking or On-Line Listen
mode; V
LxGND, LxBAT and HxL
Active mode, On-line, Partial
Networking or On-Line Listen
mode; V
HxBAT and HxVCC
Active mode, On-line, Partial
Networking or On-Line Listen
mode; V
Active mode; V
OL
OH
OL
OL
TXDC
OH
OL
BAT14
SPI bit GSTHC = logic 0
SPI bit GSTHC = logic 1
= 20 μA; V
Rev. 06 — 9 March 2010
= 0.4 V
= 0.4 V
= 0.4 V
= V
= V
= 0 V
= 5.5 V to 27 V; V
V1
V1
V2
V2
V2
V2
− 0.4 V
− 0.4 V
= 5 V; no failures
= 5 V; bus failures
= 5 V; bus failures
= 5 V
V1
V2
= 1.2 V
= 5 V
Fault-tolerant CAN/LIN fail-safe system basis chip
BAT42
≥
V
BAT14
Min
−0.3
−20
1.6
0
1.6
0.7 × V
−0.3
5
−25
1.6
−3.5
1.5
3.15
6.5
−1.25
−2.0
−
1 V; unless otherwise specified. All
V1
Typ
-
-
-
-
-
-
-
12
-
-
−3.2
1.7
3.3
7.1
−0.75
−1.5
UJA1061
© NXP B.V. 2010. All rights reserved.
Max
+0.3 ×
V
−1.6
20
0.4
15
V
+0.3 ×
V
25
−1.6
25
−2.9
1.85
3.45
8.0
−0.25
−1.0
V1
V1
V1
+ 0.3 V
Unit
V
mA
mA
V
mA
V
kΩ
mA
mA
V
V
V
V
V
V
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