UJA1061TW,512 NXP Semiconductors, UJA1061TW,512 Datasheet - Page 62

• Manufacturer Part Number: UJA1061TW,512
• Manufacturer: NXP Semiconductors

Specifications of UJA1061TW,512

• Number Of Transceivers: 1
• Power Down Mode: Sleep/Standby
• Operating Supply Voltage (min): 5.5V
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 27.
T
voltages are defined with respect to ground. Positive currents flow into the IC.
UJA1061_6
Product data sheet
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
BUS(fail)(recover)
TXDC(dom)
CANH(d1)
CANL(d1)
CANH(rec)
CANL(rec)
CANH(d2)
CANL(d2)
CANL(dom)
timeout
offline
off-line(ext)
vj
=
−
40
,
,
,
°
C to + 150
Dynamic characteristics
Parameter
bus failure recovery
time
TXDC permanent
dominant disable time
minimum dominant
time first pulse for
wake-up on pins
CANH, CANL
minimum recessive
time pulse (after first
dominant) for
wake-up on pins
CANH, CANL
minimum dominant
time second pulse for
wake-up on pins
CANH, CANL
CANL dominant time
entering Normal
mode and TXDC
goes dominant
time-out period
between wake-up
message and confirm
message
required recessive or
dominant time for
entering off-line
extended minimum
time before entering
Off-line mode
°
C; V
BAT42
= 5.5 V to 52 V; V
[1]
Conditions
bus failure HxBAT
bus failure HxVCC
bus failures LxGND and HxL;
Active mode, On-line and
Selective Sleep mode;
V
bus failures LxGND and HxL
bus failure LxBAT; Active
mode, On-line and Selective
Sleep mode; V
continuously dominant
clamped CAN-bus Active
mode, On-line and Selective
Sleep mode; V
Active mode, On-line and
Selective Sleep mode;
V
off-line
off-line
off-line
V
after entering Active mode
On-line Listen mode
On-line or Selective Sleep
mode; COTC = logic 0;
CMC = logic 0
On-line or Selective Sleep
mode; COTC = logic 1;
CMC = logic 0
On-line or On-line Listen mode
after CAN wake-up event;
TXDC = V
activity
…continued
V2
V2
CANL
All information provided in this document is subject to legal disclaimers.
= 5 V
= 5 V; TXDC = logic 0 V
> 8 V, first dominant bit
BAT14
V1
Rev. 06 — 9 March 2010
; V2D = 1; no bus
V2
V2
= 5.5 V to 27 V; V
= 5 V
= 5 V
Fault-tolerant CAN/LIN fail-safe system basis chip
BAT42
Min
125
0.3
7
0.3
125
1
1.5
7
3
0
3
115
50
200
400
≥
V
BAT14
−
1 V; unless otherwise specified. All
-
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UJA1061
Max
750
1.6
38
1.6
750
5
6
38
10
4
10
285
66
265
530
© NXP B.V. 2010. All rights reserved.
Unit
μs
ms
μs
ms
μs
μs
ms
μs
μs
μs
μs
ms
ms
ms
ms
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