UJA1061TW,512 NXP Semiconductors, UJA1061TW,512 Datasheet - Page 28

• Manufacturer Part Number: UJA1061TW,512
• Manufacturer: NXP Semiconductors

Specifications of UJA1061TW,512

• Number Of Transceivers: 1
• Power Down Mode: Sleep/Standby
• Operating Supply Voltage (min): 5.5V
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
UJA1061_6
Product data sheet
Fig 14. SPI timing protocol
SDO
SCS
SCK
SDI
6.13.1 SPI register mapping
6.13 SPI interface
floating
X
The Serial Peripheral Interface (SPI) provides the communication link with the
microcontroller, supporting multi-slave and multi-master operation. The SPI is configured
for full duplex data transfer, so status information is returned when new control data is
shifted in. The interface also offers a read-only access option, allowing registers to be
read back by the application without changing the register content.
The SPI uses four interface signals for synchronization and data transfer:
Bit sampling is performed on the falling clock edge and data is shifted on the rising clock
edge; see
To protect against wrong or illegal SPI instructions, the SBC detects the following SPI
failures:
Any control bit which can be set by software is readable by the application. This allows
software debugging as well as control algorithms to be implemented.
Watchdog serving and mode setting is performed within the same access cycle; this only
allows an SBC mode change whilst serving the watchdog.
X
•
•
•
•
•
•
•
sampled
SCS - SPI chip select; active LOW
SCK - SPI clock; default level is LOW due to low-power concept
SDI - SPI data input
SDO - SPI data output; floating when pin SCS is HIGH
SPI clock count failure (wrong number of clock cycles during one SPI access): only
16 clock periods are allowed within one SCS cycle. Any deviation from the 16 clock
cycles results in an SPI failure interrupt, if enabled. The access is ignored by the SBC.
In Start-up and Restart mode a reset is forced instead of an interrupt
Forbidden mode changes according to
Illegal Mode register code. Undefined operating mode or watchdog period coding
results in an immediate system reset; see
01
MSB
MSB
Figure
02
All information provided in this document is subject to legal disclaimers.
14.
14
14
Rev. 06 — 9 March 2010
03
13
13
04
Fault-tolerant CAN/LIN fail-safe system basis chip
12
12
Figure 3
Section 6.13.3
15
01
01
result in an immediate system reset
16
LSB
LSB
UJA1061
© NXP B.V. 2010. All rights reserved.
floating
mce634
X
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