DEMO9S08LIN Freescale, DEMO9S08LIN Datasheet - Page 85

• Manufacturer Part Number: DEMO9S08LIN
• Manufacturer: Freescale

Specifications of DEMO9S08LIN

• Lead Free Status / RoHS Status: Compliant

6.2.2
Associated with the parallel I/O ports is a set of registers located in the high page register space that operate
independently of the parallel I/O registers. These registers are used to control pullups, slew rate, and drive
strength for the associated pins and may be used in conjunction with the peripheral functions on these pins
for most modules.
The pins associated with port A are controlled by the registers in this section. These registers control the
pin pullup, slew rate and drive strength of the port A pins independent of the parallel I/O registers.
6.2.2.1
An internal pullup device can be enabled for each port pin by setting the corresponding bit in the pullup
enable register (PTAPEn). The pullup device is disabled if the pin is configured as an output by the parallel
I/O control logic or any shared peripheral function regardless of the state of the corresponding pullup
enable register bit. The pullup device is also disabled if the pin is controlled by an analog function.
Freescale Semiconductor
PTAPE[7:0]
Reset
Field
7:0
W
R
PTAPE7
Port A Control Registers
Internal Pullup Enable (
Pullup Enable for Port A Bits — For port A pins that are inputs, these read/write control bits determine whether
internal pullup devices are enabled provided the corresponding PTADDn is 0. For port A pins that are configured
as outputs, these bits are ignored and the internal pullup devices are disabled. When any of bits 7 through 0 of
port A are enabled as KBI inputs and are configured to detect rising edges/high levels, the pullup enable bits
enable pulldown rather than pullup devices.
0 Internal pullup device disabled.
1 Internal pullup device enabled.
0
7
PTAPE6
0
6
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
Figure 6-7. Pullup Enable for Port A (PTAPE)
Table 6-3. PTAPE Field Descriptions
PTAPE5
0
5
PTAPE)
PTAPE4
0
4
Description
PTAPE3
3
0
PTAPE2
0
2
Chapter 6 Parallel Input/Output
PTAPE1
0
1
PTAPE0
0
0
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