DEMO9S08LIN Freescale, DEMO9S08LIN Datasheet - Page 84

• Manufacturer Part Number: DEMO9S08LIN
• Manufacturer: Freescale

Specifications of DEMO9S08LIN

• Lead Free Status / RoHS Status: Compliant

Chapter 6 Parallel Input/Output
6.2.1.1
Port A parallel I/O function is controlled by the data and data direction registers in this section.
6.2.1.2
84
PTADD[7:0]
PTAD[7:0]
Reset
Reset
Field
Field
7:0
7:0
W
W
R
R
PTADD7
PTAD7
Port A Data Registers (PTAD)
Port A Data Direction Registers (PTADD)
Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for
PTAD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.
0
0
7
7
PTADD6
PTAD6
0
0
6
6
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
Figure 6-5. Data Direction for Port A (PTADD)
Figure 6-2. Port A Data Register (PTAD)
Table 6-2. PTADD Field Descriptions
PTADD5
Table 6-1. PTAD Field Descriptions
PTAD5
0
0
5
5
PTADD4
PTAD4
0
0
4
4
Description
Description
PTADD3
PTAD3
3
0
3
0
PTADD2
PTAD2
0
0
2
2
PTADD1
Freescale Semiconductor
PTAD1
0
0
1
1
PTADD0
PTAD0
0
0
0
0