DEMO9S08LIN Freescale, DEMO9S08LIN Datasheet - Page 301

• Manufacturer Part Number: DEMO9S08LIN
• Manufacturer: Freescale

Specifications of DEMO9S08LIN

• Lead Free Status / RoHS Status: Compliant

Chapter 17
Development Support
17.1
This chapter describes the single-wire background debug mode (BDM), which uses the on-chip
background debug controller (BDC) module, and the independent on-chip real-time in-circuit emulation
(ICE) system, which uses the on-chip debug (DBG) module.
17.1.1
Features of the BDC module include:
Features of the ICE system include:
Freescale Semiconductor
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Single pin for mode selection and background communications
BDC registers are not located in the memory map
SYNC command to determine target communications rate
Non-intrusive commands for memory access
Active background mode commands for CPU register access
GO and TRACE1 commands
BACKGROUND command can wake CPU from stop or wait modes
One hardware address breakpoint built into BDC
Oscillator runs in stop mode, if BDC enabled
COP watchdog disabled while in active background mode
Two trigger comparators: Two address + read/write (R/W) or one full address + data + R/W
Flexible 8-word by 16-bit FIFO (first-in, first-out) buffer for capture information:
— Change-of-flow addresses or
— Event-only data
Two types of breakpoints:
— Tag breakpoints for instruction opcodes
— Force breakpoints for any address access
Nine trigger modes:
— Basic: A-only, A OR B
— Sequence: A then B
— Full: A AND B data, A AND NOT B data
— Event (store data): Event-only B, A then event-only B
— Range: Inside range (A ≤ address ≤ B), outside range (address < A or address > B)
Introduction
Features
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
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