DEMO9S08LIN Freescale, DEMO9S08LIN Datasheet - Page 133

• Manufacturer Part Number: DEMO9S08LIN
• Manufacturer: Freescale

Specifications of DEMO9S08LIN

• Lead Free Status / RoHS Status: Compliant

9.3.4.1
If LCDDRMS bit in the LCDCMD register is deasserted, the LCDRAM register accesses a register bank
that controls the on/off state for frontplane drivers.
9.3.4.2
If LCDDRMS in the LCDCMD register is asserted, the LCDRAM register accesses a register bank that
controls the blink enables/disables for each individual LCD segment
9.3.5
Read: anytime
Write: anytime.It is recommended that CLKADJ[5:0], DIV16, and SOURCE not be modified while the
LCDEN bit is asserted.
Freescale Semiconductor
FP[n]BP[x]
FP[n]BP[x]
Reset
Field
Field
W
R
SOURCE
LCD Clock Source Register (LCDCLKS)
Segment On — If LCDDRMS in the LCDCMD is deasserted (LCDDRMS=0), the FP[n]BP[x] bit in the LCDRAM
registers controls on/off state for the LCD segment connected between FP[n] and BP[x].Asserting the FP[n]BP[x]
bit displays (turns on) the LCD segment connected between FP[n] and BP[x].
0 LCD segment off.
1 LCD segment on.
LCD Segment Blink Enable — If LCDDRMS bit in the LCDCMD is asserted (LCDDRMS=1), the FP[n]BP[x] bit
in the LCDRAM registers controls blink mode enable/disable state for the LCD segment connected between
FP[n] and BP[x].Asserting the FP[n]BP[x] bit enable the blink mode for the LCD segment connected between
FP[n] and BP[x] if the associated bit when LCDDRMS = 0 is also set.
0 Disables blink enable for LCD segment.
1 Enables blink enable for LCD segment.
LCDRAM Registers as On/Off Selector (LCDDRMS = 0)
LCDRAM Registers as Blink Enable/Disable (LCDDRMS = 1)
0
7
Table 9-7. LCDRAM Field Descriptions (when LCDDRMS = 0)
Table 9-8. LCDRAM Field Descriptions (when LCCDRMS = 1)
DIV16
0
6
Figure 9-6. LCD Clock Source Register (LCDCLKS)
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
CLKADJ5
0
5
CLKADJ4
0
4
Description
Description
CLKADJ3
3
0
Chapter 9 Liquid Crystal Display Driver (S08LCDV1)
.
CLKADJ2
1
2
CLKADJ1
0
1
CLKADJ0
1
0
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