DEMO9S08LIN Freescale, DEMO9S08LIN Datasheet - Page 203

• Manufacturer Part Number: DEMO9S08LIN
• Manufacturer: Freescale

Specifications of DEMO9S08LIN

• Lead Free Status / RoHS Status: Compliant

11.3.2
The two read-only TPM counter registers contain the high and low bytes of the value in the TPM counter.
Reading either byte (TPMxCNTH or TPMxCNTL) latches the contents of both bytes into a buffer where
they remain latched until the other byte is read. This allows coherent 16-bit reads in either order. The
coherency mechanism is automatically restarted by an MCU reset, a write of any value to TPMxCNTH or
TPMxCNTL, or any write to the timer status/control register (TPMxSC).
Reset clears the TPM counter registers.
Freescale Semiconductor
Reset
W
R
Bit 15
Timer x Counter Registers (TPMxCNTH:TPMxCNTL)
1
2
0
7
The maximum frequency that is allowed as an external clock is one-fourth of the bus
frequency.
If the external clock input is shared with channel n and is selected as the TPM clock source,
the corresponding ELSnB:ELSnA control bits should be set to 0:0 so channel n does not try
to use the same pin for a conflicting function.
CLKSB:CLKSA
PS2:PS1:PS0
0:0
0:1
1:0
1:1
Figure 11-4. Timer x Counter Register High (TPMxCNTH)
14
0
6
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
Table 11-2. TPM Clock Source Selection
Table 11-3. Prescale Divisor Selection
Any write to TPMxCNTH clears the 16-bit counter.
13
0
5
TPM Clock Source to Prescaler Input
No clock selected (TPMx disabled)
12
0
4
External source (TPMxCLK)
Fixed system clock (XCLK)
Bus rate clock (BUSCLK)
TPM Clock Source Divided-By
11
3
0
Chapter 11 Timer/Pulse-Width Modulator (S08TPMV2)
128
16
32
64
1
2
4
8
10
0
1,2
2
9
0
1
Bit 8
0
0
203