DEMO9S08LIN Freescale, DEMO9S08LIN Datasheet - Page 182

• Manufacturer Part Number: DEMO9S08LIN
• Manufacturer: Freescale

Specifications of DEMO9S08LIN

• Lead Free Status / RoHS Status: Compliant

Chapter 10 Internal Clock Generator (S08ICGV4)
entering off mode. If CLKS bits are set to 01 or 11 coming out of the Off state, the ICG enters this mode
until ICGDCLK is stable as determined by the DCOS bit. After ICGDCLK is considered stable, the ICG
automatically closes the loop by switching to FLL engaged (internal or external) as selected by the CLKS
bits.
10.5.3
FLL engaged internal (FEI) is entered when any of the following conditions occur:
In FLL engaged internal mode, the reference clock is derived from the internal reference clock
ICGIRCLK, and the FLL loop will attempt to lock the ICGDCLK frequency to the desired value, as
selected by the MFD bits.
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CLKS bits are written to 01
The DCO clock stabilizes (DCOS = 1) while in SCM upon exiting the off state with CLKS = 01
FLL Engaged, Internal Clock (FEI) Mode
DCOS
COUNTER ENABLE
CLKST
SUBTRACTOR
Figure 10-13. Detailed Frequency-Locked Loop Block Diagram
REFERENCE
DIVIDER (/7)
RANGE
LOCK
MFD
RANGE
OVERFLOW
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
LOSS OF CLOCK
LOLS
DETECTOR
LOCK AND
LOCS
ICGIRCLK
ERCS
DIGITAL
CLKST
FILTER
LOOP
FLT
LOCD
COUNTER
PULSE
ICGIF
CONTROLLED
OSCILLATOR
FLL ANALOG
DIGITALLY
INTERRUPT
RESET AND
CIRCUIT
SELECT
CLOCK
CONTROL
CLKS
LOLRE
ICGDCLK
ICG2DCLK
1x
2x
LOCRE
FREQUENCY
DIVIDER (R)
REDUCED
RFD
Freescale Semiconductor
FREQUENCY-
LOOP (FLL)
LOCKED
ICGOUT
RESET
IRQ