DEMO9S08LIN Freescale, DEMO9S08LIN Datasheet - Page 112

• Manufacturer Part Number: DEMO9S08LIN
• Manufacturer: Freescale

Specifications of DEMO9S08LIN

• Lead Free Status / RoHS Status: Compliant

Chapter 8 Central Processor Unit (S08CPUV2)
8.5
Instruction Set Summary Nomenclature
The nomenclature listed here is used in the instruction descriptions in
Operators
CPU registers
Memory and addressing
M:M + 0x0001= A 16-bit value in two consecutive memory locations. The higher-order (most
Condition code register (CCR) bits
CCR activity notation
112
CCR
PCH
PCL
PC
SP
←
( )
M
⊕
H
H
N
C
&
A
X
V
Z
HCS08 Instruction Set Summary
+
–
×
÷
–
|
:
I
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
Contents of register or memory location shown inside parentheses
Is loaded with (read: “gets”)
Boolean AND
Boolean OR
Boolean exclusive-OR
A memory location or absolute data, depending on addressing mode
significant) 8 bits are located at the address of M, and the lower-order (least
significant) 8 bits are located at the next higher sequential address.
Two’s complement overflow indicator, bit 7
Half carry, bit 4
Interrupt mask, bit 3
Negative indicator, bit 2
Zero indicator, bit 1
Carry/borrow, bit 0 (carry out of bit 7)
Bit not affected
Multiply
Divide
Concatenate
Add
Negate (two’s complement)
Accumulator
Condition code register
Index register, higher order (most significant) 8 bits
Index register, lower order (least significant) 8 bits
Program counter
Program counter, higher order (most significant) 8 bits
Program counter, lower order (least significant) 8 bits
Stack pointer
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
Table
8-2.
Freescale Semiconductor