DEMO9S08LIN Freescale, DEMO9S08LIN Datasheet - Page 342

• Manufacturer Part Number: DEMO9S08LIN
• Manufacturer: Freescale

Specifications of DEMO9S08LIN

• Lead Free Status / RoHS Status: Compliant

Appendix A Electrical Characteristics
A.10.1
1
2
3
4
342
Bus frequency (t
Real-time interrupt internal oscillator period
External reset pulse width
Reset low drive
Active background debug mode latch setup time
Active background debug mode latch hold time
IRQ pulse width
Port rise and fall time (load = 50 pF)
This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
When any reset is initiated, internal circuitry drives the reset pin low for about 34 cycles of f
on the reset pin about 38 cycles later to distinguish external reset requests from internal requests.
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
Timing is shown with respect to 20% V
Slew rate control disabled
Slew rate control enabled
Control Timing
(2)
(3)
cyc
= 1/f
RESET PIN
Parameter
Figure A-13. Active Background Debug Mode Latch Timing
Bus
(1)
)
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
BKGD/MS
RESET
DD
(4)
and 80% V
Table A-13. Control Timing
Figure A-12. Reset Timing
t
MSSU
DD
levels. Temperature range –40°C to 85°C.
t
Symbol
Rise
t
t
t
MSSU
t
rstdrv
t
f
extrst
t
MSH
t
ILIH
Bus
RTI
extrst
, t
Fall
f
f
1.5 x t
Self_reset
Self_reset
1.5 x
34 x
Min
700
dc
25
25
—
—
cyc
t
MSH
Self_reset
Typical
30
—
3
and then samples the level
Freescale Semiconductor
1300
Max
20
—
—
—
—
—
MHz
Unit
μs
ns
ns
ns
ns
ns
ns