DEMO9S08LIN Freescale, DEMO9S08LIN Datasheet - Page 220

• Manufacturer Part Number: DEMO9S08LIN
• Manufacturer: Freescale

Specifications of DEMO9S08LIN

• Lead Free Status / RoHS Status: Compliant

Chapter 12 Serial Communications Interface (S08SCIV3)
12.2.2
This read/write register is used to control various optional features of the SCI system.
220
SCISWAI
SBR[7:0]
Reset
LOOPS
WAKE
RSRC
Field
Field
7:0
ILT
M
7
6
5
4
3
2
W
R
LOOPS
SCI Control Register 1 (SCIC1)
Baud Rate Modulo Divisor — These 13 bits are referred to collectively as BR, and they set the modulo divide
rate for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to reduce supply
current. When BR = 1 to 8191, the SCI baud rate = BUSCLK/(16×BR). See also BR bits in
Loop Mode Select — Selects between loop back modes and normal 2-pin full-duplex modes. When
LOOPS = 1, the transmitter output is internally connected to the receiver input.
0 Normal operation — RxD and TxD use separate pins.
1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See
SCI Stops in Wait Mode
0 SCI clocks continue to run in wait mode so the SCI can be the source of an interrupt that wakes up the CPU.
1 SCI clocks freeze while CPU is in wait mode.
Receiver Source Select — This bit has no meaning or effect unless the LOOPS bit is set to 1. When
LOOPS = 1, the receiver input is internally connected to the TxD pin and RSRC determines whether this
connection is also connected to the transmitter output.
0 Provided LOOPS = 1, RSRC = 0 selects internal loop back mode and the SCI does not use the RxD pins.
1 Single-wire SCI mode where the TxD pin is connected to the transmitter output and receiver input.
9-Bit or 8-Bit Mode Select
0 Normal — start + 8 data bits (LSB first) + stop.
1 Receiver and transmitter use 9-bit data characters
Receiver Wakeup Method Select — Refer to
information.
0 Idle-line wakeup.
1 Address-mark wakeup.
Idle Line Type Select — Setting this bit to 1 ensures that the stop bit and logic 1 bits at the end of a character
do not count toward the 10 or 11 bit times of the logic high level by the idle line detection logic. Refer to
Section 12.3.3.2.1, “Idle-Line
0 Idle character bit count starts after start bit.
1 Idle character bit count starts after stop bit.
0
7
RSRC
start + 8 data bits (LSB first) + 9th data bit + stop.
bit.) RxD pin is not used by SCI.
SCISWAI
0
6
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
Table 12-2. SCIBDL Register Field Descriptions
Table 12-3. SCIC1 Register Field Descriptions
Figure 12-7. SCI Control Register 1 (SCIC1)
RSRC
Wakeup” for more information.
0
5
M
0
4
Section 12.3.3.2, “Receiver Wakeup
Description
Description
WAKE
3
0
ILT
0
2
Operation” for more
Freescale Semiconductor
PE
0
1
Table
12-1.
PT
0
0