HC230F1020 Altera, HC230F1020 Datasheet - Page 76
HC230F1020
Manufacturer Part Number
HC230F1020
Description
Manufacturer
Altera
Datasheet
1.HC230F1020.pdf
(228 pages)
Specifications of HC230F1020
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HC230F1020ANQ
Manufacturer:
Discera
Quantity:
2 000
- Current page: 76 of 228
- Download datasheet (4Mb)
HardCopy Series Handbook, Volume 1
4–34
Notes to
(1)
(2)
(3)
1.5-V Differential
HSTL Class I
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
3.3-V LVCMOS
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I OCT 50 Ω
SSTL-18 Class II OCT 25 Ω
1.5-V HSTL
Class I
1.8-V HSTL
Class I
1.8-V HSTL
Class II
Table 4–37. HardCopy II Maximum Output Clock Rate for HC210, HC220, HC230 and HC240 Devices (OCT)
Note (1)
Table 4–38. HardCopy II Maximum Output Clock Rate for HC210W using OCT
I/O Standard
I/O Standard
The toggle rate applies to 0 pF output load for all I/O standards except for LVDS and HyperTransport technology
on row I/O pins. For LVDS and HyperTransport technology on row I/O pins, the toggle rates apply to load from
0 to 5 pF.
CLK [1, 3, 9, 11] and FPLL_CLK are dedicated input clocks, and excluded from this table.
Like Stratix II devices, differential HSTL and SSTL is supported only on the column CLK, PLL_OUT and memory
interface DQS IOE pins. For HC210 and HC220, only the top column clock pins support Differential HSTL and
SSTL.
Table
(Part 2 of 2)
(3)
4–37:
OCT 50 Ω
OCT 50 Ω
OCT 50 Ω
OCT 50 Ω
OCT 50 Ω
OCT 50 Ω
OCT 50 Ω
OCT 25 Ω
OCT 50 Ω
OCT 50 Ω
OCT 50 Ω
Strength
Strength
Drive
Drive
Interface
Interface
Memory
Memory
IOEs
IOEs
550
280
245
290
245
190
280
280
230
220
190
270
210
Speed
Speed
High
High
IOEs
IOEs
280
245
290
245
190
—
—
—
—
—
—
—
—
Column
Column
Bottom
Bottom
General Purpose
General Purpose
280
245
290
245
190
—
—
—
—
—
—
—
—
IOEs
IOEs
Right
Right
Row
Row
280
245
290
245
190
—
—
—
—
—
—
—
—
CLK [0,
CLK [0,
10]
10]
2, 8,
2, 8,
280
245
290
245
190
—
—
—
—
—
—
—
—
(2)
(2)
Notes
12..15]
12..15]
[4..7,
[4..7,
CLK
CLK
550
280
245
290
245
190
280
280
230
220
190
270
210
(1),
Altera Corporation
PLL_OUT
PLL_OUT
(4)
September 2008
550
280
245
290
245
190
280
280
230
220
190
270
210
(Part 1 of 2)
MHz
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
Related parts for HC230F1020
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: