HC230F1020 Altera, HC230F1020 Datasheet - Page 163

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HC230F1020

Manufacturer Part Number
HC230F1020
Description
Manufacturer
Altera
Datasheet

Specifications of HC230F1020

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Summary
Altera Corporation
September 2008
set_input_delay –clock ref_clk –min 2 [get_ports data_in]
# Output delay of 6ns (max) & 2ns (min) for bus data_out[1:0]
set_output_delay –clock ref_clk –max 6 [get_ports data_out]
set_output_delay –clock ref_clk –min 2 [get_ports data_out]
# Don’t care about timing on the resetn net. Set as false path
set_false_path -from [get_ports resetn]
## End of timing_assignments.tcl
Timing Assignments Script timing_assignments.tcl
If you are using Classic Timing Analyzer, the
timing_assignments.tcl script is run from the top-level script,
demo_design.tcl. This script applies timing constraints for the system
clock, ref_clk, and I/O-to-core timing specifications.
## timing_assignments.tcl
create_base_clock –fmax 10.0ns –target ref_clk ref_clk
set_instance_assignment -name LATE_CLOCK_LATENCY 3ns -to ref_clk
set_instance_assignment -name EARLY_CLOCK_LATENCY 2ns -to ref_clk
set_clock_uncertainty –hold –to ref_clk 0.250ns
set_clock_uncertainty –setup –to ref_clk 0.250ns
# Input delay of 6ns (max) & 2ns (min) for bus data_in[1:0]
set_input_delay –clk_ref ref_clk –max –to data_in 6.0ns
set_input_delay –clk_ref ref_clk –min –to data_in 2.0ns
# Output delay of 6ns (max) & 2ns (min) for bus data_out[1:0]
set_output_delay –clk_ref ref_clk –max –to data_out 6.0ns
set_output_delay –clk_ref ref_clk –min –to data_out 2.0ns
# Don’t care about timing on the resetn net. Set as false path
set_timing_cut_assignment -from resetn
## End of timing_assignments.tcl
This chapter introduced script-based design for HardCopy II devices
using the Quartus II interactive Tcl shell. This approach provides you
with an alternative to GUI-based design for certain situations such as
remote-terminal Quartus II execution, design flow automation, or even if
you are simply more comfortable operating in a scripting environment.
Summary
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