HC230F1020 Altera, HC230F1020 Datasheet - Page 111

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

Performing
ECOs with
Change
Manager and
Chip Planner
Altera Corporation
September 2008
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For information about using Quartus II Incremental Compilation, refer
to the Quartus II Incremental Compilation for Hierarchical and Team-Based
Design chapter in volume 1 of the Quartus II Handbook.
Maximum Fanout Assignments
This feature is supported beginning in Quartus II 6.1. In order to meet
timing, it may be necessary to limit the number of fanouts of a net in your
design. You can limit the maximum fanout of a given net by using this
feature.
For example, you can use the following Tcl command to enable the
maximum fanout setting:
set_instance_assignment -name MAX_FANOUT <number>
- to\ <net name>
For example, if you want to limit the maximum fanout of net called
"m3122_combout_1" to 25, the Tcl command is as follows:
set_instance_assignment -name MAX_FANOUT 25 -to\
m3122_combout_1
As designs grow larger and larger in density, the need to analyze the
design for performance, routing congestion, logic placement, and
executing Engineering Change Orders (ECOs) becomes critical. In
addition to design analysis, you can use various bottom-up and
top-down flows to implement and manage the design. This becomes
difficult to manage since ECOs are often implemented as last minute
changes to your design.
The first compilation after migration to a companion device requires
a full compilation (all partitions are compiled), but subsequent
compilations can be incremental if changes to the source RTL are not
required. For example, PLL phase changes can be implemented
incrementally if the blocks are partitioned.
The entire design must be migrated between Stratix II and
HardCopy II companion devices. The Quartus II software does not
support migration of partitions between companion devices.
Bottom-up Quartus II Incremental Compilation is not supported for
HardCopy II devices.
Physical Synthesis can be run on individual partitions within the
originating device only. The resulting optimizations are preserved in
the migration to the companion device.
Performing ECOs with Change Manager and Chip Planner
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