HC230F1020 Altera, HC230F1020 Datasheet - Page 168

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

HardCopy Series Handbook, Volume 1
7–4
I/O Path Timing
The actual timing and parametric characteristics of I/O cells in
HardCopy II devices are very similar to those in Stratix II devices. You
should expect, however, to see differences in I/O signal path timing.
These differences are primarily because of timing differences in
core-to-I/O and clock distribution.
For core-to-I/O timing, one of the largest influencing factors is the timing
behavior of signal paths, as described in the
Timing”
different between HardCopy II and Stratix II devices.
The other major influence on I/O timing is the clock distribution
differences between HardCopy II and Stratix II devices. Shorter, faster
clock trees, custom clock tree buffering and custom routing of leaf
sub-trees in HardCopy II mean that insertion delays, latencies, skew
characteristics, jitter, and PLL compensation are different from the Stratix
II FPGA. The effect of this is described in the
section.
Clock Distribution Effects
The HardCopy II structured ASIC has a clock distribution scheme that is
similar to that in Stratix II FPGAs with some notable differences:
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These physical differences affect clock distribution characteristics across
the device. Timing characteristics most affected are:
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In general, clock tree latencies are smaller in the HardCopy II device
because of shorter routing length and the absence of
SRAM-programmable switches. As a result, you should expect that any
clock insertion delays that are modeled will also be shorter.
There are no SRAM-programmable switches and routing
connections
Reduced die-size means shorter overall clock tree routing length
Leaf sub-trees of clock networks are custom routed using
customized metal mask layers
Clock tree latency and clock insertion delay
Clock skew
Clock jitter
PLL compensation delays
section. In general, core-to-I/O and I/O-to-core timing are
“Internal Register-to-Register
“Clock Distribution Effects”
Altera Corporation
September 2008