HC230F1020 Altera, HC230F1020 Datasheet - Page 25

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

Altera Corporation
September 2008
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
LVPECL
Table 2–9. HardCopy II Supported I/O Standards (Part 3 of 3)
I/O Standard
Pseudo-differential HSTL and SSTL inputs only use the positive-polarity input in the speed path. The negative
input is not connected internally. Pseudo-differential HSTL and SSTL outputs use two single-ended outputs with
the second output programmed as inverted. This is similar to a Stratix II device implementation.
The PCI clamping diode is only supported on the I/O pins on the top and bottom sides of the device.
This I/O standard is only supported on the DQS, CLK and PLL_FB input pins or on the PLL_OUT output pins.
This I/O standard is only supported on the bottom CLK and PLL_FB input pins or on the bottom PLL_OUT output
pins.
This I/O standard is only supported on the CLK and PLL_FB input pins or on the PLL_OUT output pins.
Also supported on CLK9 and CLK11 pins.
This I/O standard is only supported on CLK and PLL_FB input pins.
LVPECL input I/O standard is supported on the top and bottom
standard is supported on the top and bottom PLL_OUT output pins. LVPECL support is similar to Stratix II devices.
Table
2–9:
Differential
Type
The three types of IOEs are located in different areas of the device and are
described in the following sections. HardCopy II devices have eight I/O
banks, just as in Stratix II FPGAs.
I/O type each bank supports.
3.3/2.5/
1.8/1.5
Input
V
CCIO
Level (V)
Output
(8)
CLK
Figures 2–4
Interface
Memory
and PLL_FB input pins. LVPECL output I/O
IOEs
(8)
Purpose IOEs
through
I/O Structure and Features
General
(8)
2–6
show which
High-Speed
Preliminary
IOEs
2–17