HC230F1020 Altera, HC230F1020 Datasheet - Page 220
HC230F1020
Manufacturer Part Number
HC230F1020
Description
Manufacturer
Altera
Datasheet
1.HC230F1020.pdf
(228 pages)
Specifications of HC230F1020
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HardCopy Series Handbook, Volume 1
Figure 8–6. Stratix II ALM Simple Registered Input and Output
8–32
datae0
datae1
dataf0
dataf1
dataa
datab
datad
datac
Combinational
Logic
ALM block with a predetermined HCell macro that implements a register
from its HardCopy II library of HCell macros. This macro entry has
predetermined timing.
Figure 8–7
Clock, Data In, and Data Out originating from a small cluster of HCells.
Unused HCells are reserved for other logic implementation or powered
down.
Figure 8–7. HardCopy II Unused HCells
shared_arith_out
shared_arith_in
shows a HardCopy II ALM register implementation showing
carry_out
carry_in
adder0
adder1
reg_chain_in
reg_chain_out
D
D
PRN
PRN
reg1
reg0
Q
Q
To General or
Local Routing
To General or
Local Routing
To General or
Local Routing
To General or
Local Routing
Altera Corporation
September 2008
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