HC230F1020 Altera, HC230F1020 Datasheet - Page 181

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

Altera Corporation
September 2008
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For a full list of available report APIs, refer to the SDC and TimeQuest API
Reference Manual.
Primary Input Port Timing
You must specify the primary input port timing constraint for every
primary input port in the design (and for the input path of every
bidirectional port). The following two subsections describe how to
constrain input port timing.
External Input Delay Specification
To constrain the input port timing, describe the external timing
environment in terms of the maximum and minimum arrival times of the
external signals that drive the primary input ports of the HardCopy series
device or FPGA.
drives the primary input port. The static timing analysis tool can use this
external input delay time to check if there is enough time for the data to
propagate to the internal nodes of the device. If there is not enough time,
a timing violation occurs.
Figure 7–8. External Timing Constraint Driving a Primary Input Port
Internal Input Delay Specification
This approach describes the acceptable maximum on-chip delay for your
design. For example, you can use this approach to describe the setup time
of a primary input to any register in the design relative to a specific clock.
Figure 7–9
which may be different for each clock domain. You may specify the
minimum on-chip delay from any primary input port to describe input
hold-time requirements.
External Device
D
dff
Q
shows a generic circuit with an on-chip setup-time constraint,
External Input Delay
Figure 7–8
Data Path
Delay
Constraining Timing of HardCopy Series Devices
shows the external timing constraint that
Primary Input to
PLD/HardCopy
Series Device
HardCopy Device or FPGA
Data Path
Delay
D
dff
7–17
Q